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31. 发明授权

US06674674B2 Method for recognizing and replacing defective memory cells in a memory 有权
标题翻译：用于识别和替换存储器中的有缺陷的存储单元的方法
公开(公告)号：US06674674B2
公开(公告)日：2004-01-06
申请号：US10164213
申请日：2002-06-06
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G11C11/401 , G11C29/38 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/52
摘要： A method for recognizing a defective memory cell in a memory having a plurality of memory cells includes directly comparing predetermined properties of the memory cells to one another. Predetermined identical information is read into each memory cell of the plurality of memory cells, and then the information stored in the plurality of memory cells is read out. For each one of the plurality of memory cells a strength of a read-out signal is determined, and the memory cells are sorted depending on the strength of the respective read-out signal.
摘要翻译：一种用于识别具有多个存储单元的存储器中的有缺陷的存储单元的方法包括将存储器单元的预定特性彼此直接比较。将预定的相同信息读入多个存储单元的每个存储单元，然后读出存储在多个存储单元中的信息。对于多个存储单元中的每一个，确定读出信号的强度，并且根据各个读出信号的强度对存储单元进行分类。

32. 发明授权

US5889420A OCD with low output capacitance 失效
标题翻译： OCD具有低输出电容
公开(公告)号：US5889420A
公开(公告)日：1999-03-30
申请号：US885329
申请日：1997-06-30
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： H03K19/0175 , H03K17/16 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361 , H03K17/164 , H03K19/00315 , H03K19/018571
摘要： An OCD circuit with stacked transistor that is gated to switch on prior to the switching on of the transistors which the stacked transistor protects. The gating of the stacked transistor results in the reduction of the total OCD output capacitance.
摘要翻译：具有堆叠晶体管的OCD电路，其被门控以在层叠晶体管保护的晶体管的接通之前导通。堆叠晶体管的选通导致总OCD输出电容的减小。

33. 发明申请

US20070230082A1 INTEGRATED CIRCUIT HAVING A PLURALITY OF EXTERNALLY FED POWER SUPPLY SYSTEMS 审中-公开
标题翻译：具有多种外部电源供电系统的集成电路
公开(公告)号：US20070230082A1
公开(公告)日：2007-10-04
申请号：US11694498
申请日：2007-03-30
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： H02H9/06
CPC分类号： G11C5/14 , G11C29/12 , G11C29/12005
摘要： An integrated circuit has at least two supply systems, each of which is connected to an individually assigned section of the integrated circuit to supply power to the relevant section. A low-pass coupler is connected between the at least two supply systems.
摘要翻译：集成电路具有至少两个供电系统，每个供应系统连接到集成电路的单独分配的部分以向相关部分供电。低通耦合器连接在至少两个供电系统之间。

34. 发明授权

US07170798B2 Controlled substrate voltage for memory switches 有权
标题翻译：存储器开关的受控衬底电压
公开(公告)号：US07170798B2
公开(公告)日：2007-01-30
申请号：US10652266
申请日：2003-08-29
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C16/04
CPC分类号： G11C5/146 , G11C11/404 , G11C11/4074 , G11C11/408
摘要： Active control of body contacts in memory devices can provide variable substrate voltages during device operation. The body contacts can be used to adjust the body bias of switches in activated memory cells, while maintaining the body bias of switches in inactive memory cells. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line (“WL”) is activated.
摘要翻译：存储器件中主体接触的主动控制可以在器件操作期间提供可变的衬底电压。身体接触可用于调节激活的存储器单元中的开关的体偏，同时保持开关在非活动存储器单元中的体偏置。这可以减少身体效应（即，由于衬底或体电压的变化引起的阈值电压的变化），并且因此可以提供改善的阵列器件性能（例如，减少的数据损坏），而字线（“WL”）是活性。

35. 发明授权

US07162382B2 Apparatus and method for calibrating signals 有权
标题翻译：用于校准信号的装置和方法
公开(公告)号：US07162382B2
公开(公告)日：2007-01-09
申请号：US10618056
申请日：2003-07-11
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G06F3/01
CPC分类号： G11C29/12015 , G11C29/028 , G11C29/14 , G11C29/50012 , G11C29/56 , G11C29/56012
摘要： The invention is directed to a device for calibrating signals, whereby at least two signal circuits are provided for generating signals. In order to calibrate the signals, elements are provided that evaluate the signals generated by the signal circuits and, dependent thereon, drive at least one of the at least two signal circuits such that the time reference of the signals generated by the signal circuits relative to one another is set corresponding to at least one prescribed value.
摘要翻译：本发明涉及用于校准信号的装置，由此提供至少两个用于产生信号的信号电路。为了校准信号，提供了评估由信号电路产生的信号并依赖于其的驱动至少两个信号电路中的至少一个的元件，使得由信号电路产生的信号的时间基准相对于彼此相对应设置为至少一个规定值。

36. 发明申请

US20060203567A1 Integrated memory circuit and method for repairing a single bit error 失效
标题翻译：用于修复单个位错误的集成存储器电路和方法
公开(公告)号：US20060203567A1
公开(公告)日：2006-09-14
申请号：US11331577
申请日：2006-01-13
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C7/10
CPC分类号： G11C29/4401 , G11C29/44 , G11C2029/0405
摘要： The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information, an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information. The test unit comprises a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array, a read-out unit which reads out data stored in the memory area, a modification unit in order to modify the bits of the read-out data in such a way that the position of each bit changes and each of the bits is inverted in order to provide the second test data, which are subsequently written to the memory area with the aid of the write unit, and a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result.
摘要翻译：本发明涉及具有存储单元阵列的集成存储器电路，该存储单元阵列包括布置在字线和位线上的存储器单元，并且具有用于修复其中一个存储器单元中的单个位错误的修复电路，该修复电路包括：错误存储器用于存储修复信息的项目，分配单元，当根据修复信息访问存储单元阵列的地址时，访问存储单元阵列的存储区域或冗余存储区域，以及测试用于确定修复信息的单元。测试单元包括写入单元，其将第一测试数据和第二测试数据连续地写入存储单元阵列的存储区域的多个存储单元;读出单元，其读出存储在存储区域中的数据，修改单元，以便以这样的方式修改读出数据的位，使得每个位的位置改变，并且每个位被反转以提供第二测试数据，随后将其写入存储区域写单元的帮助和比较器单元，以便将写入第二测试数据之后读出的数据与预期数据进行比较，并根据比较结果提供修复信息。

37. 发明申请

US20060203559A1 Memory device with customizable configuration 审中-公开
标题翻译：具有可定制配置的内存设备
公开(公告)号：US20060203559A1
公开(公告)日：2006-09-14
申请号：US11067914
申请日：2005-02-28
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C11/34
CPC分类号： G11C7/1045 , G11C7/1048 , G11C11/4093 , G11C17/165
摘要： One embodiment of the present invention relates to a memory device in a package comprising a plurality of data output ports, a plurality of internal data lines for providing data to and from a memory unit, a switching unit which is operable, depending on an operational mode, either to connect a first number of the internal data lines to a first number of the plurality of data output ports in a first operational mode or to connect a second number of the internal data lines to a second number of the plurality data output ports in a second operational mode, wherein the first number is smaller than the second number; and a mode selector unit which is connected to the switching unit to set the operational mode of the switching unit, wherein the mode selector unit includes a programmable storage unit for writing mode data from externally and wherein the operational mode is determined depending on the mode data.
摘要翻译：本发明的一个实施例涉及包括多个数据输出端口，用于向存储器单元提供数据和从存储器单元提供数据的多个内部数据线的封装中的存储器件，根据操作模式可操作的切换单元或者在第一操作模式中将第一数量的内部数据线连接到多个数据输出端口中的第一数量，或者将第二数量的内部数据线连接到第二数量的多个数据输出端口第二操作模式，其中所述第一数量小于所述第二数量; 以及模式选择器单元，其连接到所述切换单元以设置所述切换单元的操作模式，其中所述模式选择器单元包括用于从外部写入模式数据的可编程存储单元，并且其中所述操作模式根据模式数据来确定。

38. 发明申请

US20060193184A1 Hub module for connecting one or more memory chips 审中-公开
标题翻译：用于连接一个或多个存储器芯片的集线器模块
公开(公告)号：US20060193184A1
公开(公告)日：2006-08-31
申请号：US11348514
申请日：2006-02-06
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： The invention relates to a hub module for connecting one or more memory chips, said module having an address input for connection to an address bus in order to receive an address of the memory area to be addressed and having an address output for connection to a further address bus, and having an address decoder unit in order to address one of the connected memory chips using an address that is applied to the address input or to apply the applied address to the address output, characterized in that the address decoder unit has a redundancy unit in order to address a redundant memory area instead of the addressed memory area in the event of a defect being detected in a memory area of the one or more connected memory chips.
摘要翻译：本发明涉及一种用于连接一个或多个存储器芯片的集线器模块，所述模块具有用于连接到地址总线的地址输入，以便接收要寻址的存储器区域的地址，并具有用于连接到另一个的地址输出并且具有地址解码器单元，以便使用应用于地址输入的地址来寻址连接的存储器芯片之一，或者将所施加的地址应用于地址输出，其特征在于，地址解码器单元具有冗余单元，以便在所述一个或多个连接的存储器芯片的存储器区域中检测到缺陷的情况下寻址冗余存储器区域而不是寻址的存储器区域。

39. 发明授权

US06940773B2 Method and system for manufacturing DRAMs with reduced self-refresh current requirements 失效
标题翻译：具有降低的自刷新电流要求的制造DRAM的方法和系统
公开(公告)号：US06940773B2
公开(公告)日：2005-09-06
申请号：US10404561
申请日：2003-04-02
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4061
摘要： A method and system for reducing self-refresh current requirements in a includes a DRAM chip that is sectioned into a number of segments. The entire DRAM chip is tested upon manufacture to determine the relative decay rates for each cell in the DRAM. For each segment, the refresh rate for that segment is selected based on the fastest decay rate for a DRAM cell in the segment. The DRAM is configured for refreshing memory cells during a self-refresh at different refresh rates for different segments. The refresh period is controlled for individual segments using techniques, such as programmable logic or fuses, to skip certain self-refresh cycles for those segments capable of operating at lower refresh rates. The refresh period in memory segments with strong memory cells can be reduced, thereby conserving current required to be drawn.
摘要翻译：用于减少自刷新电流要求的方法和系统包括被划分成多个段的DRAM芯片。整个DRAM芯片在制造时进行测试，以确定DRAM中每个单元的相对衰减速率。对于每个段，基于片段中的DRAM单元的最快的衰减速率来选择该段的刷新率。 DRAM被配置为在针对不同段的不同刷新率的自刷新期间刷新存储器单元。使用诸如可编程逻辑或熔丝的技术来针对各个段来控制刷新周期，以跳过能够以较低刷新率操作的那些段的某些自刷新周期。可以减少具有较强存储单元的存储器段中的刷新周期，从而节省需要绘制的电流。

40. 发明申请

US20050018469A1 Array transistor amplification method and apparatus for dynamic random access memory 失效
公开(公告)号：US20050018469A1
公开(公告)日：2005-01-27
申请号：US10625962
申请日：2003-07-24
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C7/06 , G11C11/4091 , H01L27/108 , G11C11/24
CPC分类号： H01L27/10897 , G11C7/06 , G11C11/4091 , H01L27/10841
摘要： As disclosed herein, a method and apparatus are provided for amplifying a signal by a transistor of an array of transistors that includes a storage cell transistor array of a dynamic random access memory (DRAM). According to the disclosed method, an array of transistors is provided including transistors of a storage cell transistor array of a dynamic random access memory array. A transistor of the array of transistors has a source or a drain coupled to a fixed potential. An input signal is applied to a gate of the transistor, whereby the transistor amplifies the input signal to provide an output signal appearing on the other of the source or drain of the transistor.

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