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    • 38. 发明授权
    • Vertical synchronizing signal detector
    • 垂直同步信号检测器
    • US4291335A
    • 1981-09-22
    • US98632
    • 1979-11-29
    • Isao NakagawaNorio Minami
    • Isao NakagawaNorio Minami
    • H04N5/10H04N9/00H04N9/793H04N9/83
    • H04N5/10
    • A composite synchronizing signal is applied to the D input terminal of a D type flip-flop. A multiplied pulse obtained by multiplying a horizontal reference signal by 40 is applied to the C input terminal thereof, the horizontal reference being in phase with the horizontal synchronizing pulse of the composite synchronizing signal. A logic product of the output of a flip-flop and the multiplied pulse is produced. Pulses in the form of the logic product are counted during a period between two adjacent horizontal reference pulses. A detection pulse is generated which rises when the count exceeds 28 and ends with the end of the later one of two adjacent horizontal reference pulses. In response to this detection pulse, a vertical synchronizing pulse is detected. The timing of the ending of the detection pulse is not affected by noise pulses.
    • 复合同步信号被施加到D型触发器的D输入端。 通过将水平参考信号乘以40获得的相乘脉冲被施加到其C输入端,水平参考与复合同步信号的水平同步脉冲相同。 产生触发器的输出和相乘的脉冲的逻辑积。 在两个相邻的水平参考脉冲之间的周期内,以逻辑积的形式计数脉冲。 产生检测脉冲,其在计数超过28时上升,并且以两个相邻的水平参考脉冲之后的一个结束而结束。 响应该检测脉冲,检测垂直同步脉冲。 检测脉冲结束的定时不受噪声脉冲的影响。