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31. 发明申请

US20120153493A1 EMBEDDED COMPONENT DEVICE AND MANUFACTURING METHODS THEREOF 有权
标题翻译：嵌入式组件设备及其制造方法
公开(公告)号：US20120153493A1
公开(公告)日：2012-06-21
申请号：US12972046
申请日：2010-12-17
申请人： CHUN-CHE LEE , YUAN-CHANG SU , MING CHIANG LEE , SHIH-FU HUANG
发明人： CHUN-CHE LEE , YUAN-CHANG SU , MING CHIANG LEE , SHIH-FU HUANG
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L25/16 , H01L23/5389 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/82 , H01L2224/04105 , H01L2224/16225 , H01L2224/24195 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2924/00014 , H01L2924/01029 , H01L2924/15153 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.
摘要翻译：嵌入式组件装置包括电子部件，其包括电接触，上图案化导电层，上图案化导电层和电子部件之间的介电层，第一电互连，下图案化导电层，导电通孔和第二电互连。电介质层具有暴露电接触的第一开口和从下图案化导电层延伸到上图案化导电层的第二开口。第一电互连从电接触延伸到上图案化导电层，并填充第一开口。第二开口具有暴露上部图案化导电层的上部和暴露下部图案化导电层的下部。导电通孔位于第二开口的下部。第二电互连填充第二开口的上部。

32. 发明授权

US07993982B2 Quad flat non-leaded package and manufacturing method thereof 有权
标题翻译：四边形非铅包装及其制造方法
公开(公告)号：US07993982B2
公开(公告)日：2011-08-09
申请号：US12556841
申请日：2009-09-10
申请人： Ming-Chiang Lee
发明人： Ming-Chiang Lee
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L21/568 , H01L23/3107 , H01L2224/48245 , H01L2224/48247 , H01L2924/181 , H01L2924/00012
摘要： A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
摘要翻译：提供了包括第一图案化导电层，第二图案化导电层，芯片，接合线和模制化合物的四边形扁平非引线封装。第一图案化导电层限定第一空间，并且第二图案化导电层限定第二空间，其中第一空间与第二空间重叠，并且第二图案化导电层的一部分围绕第二空间。芯片设置在第二图案化导电层上。接合线连接在芯片和第二图案化导电层之间。模制化合物封装第二图案化导电层，芯片和接合线。此外，还提供了制造四边形非铅包装的方法。

33. 发明申请

US20110169150A1 Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof 有权
标题翻译：具有单面基板的半导体封装设计和制造方法
公开(公告)号：US20110169150A1
公开(公告)日：2011-07-14
申请号：US13006340
申请日：2011-01-13
申请人： Yuan-Chang Su , Shih-Fu Huang , Chia-Cheng Chen , Tzu-Hui Chen , Kuang-Hsiung Chen , Pao-Ming Hsieh , Ming Chiang Lee , Bernd Karl Appelt
发明人： Yuan-Chang Su , Shih-Fu Huang , Chia-Cheng Chen , Tzu-Hui Chen , Kuang-Hsiung Chen , Pao-Ming Hsieh , Ming Chiang Lee , Bernd Karl Appelt
IPC分类号： H01L23/495 , H01L21/60 , H05K3/10
CPC分类号： H01L24/14 , H01L21/4857 , H01L21/563 , H01L21/6835 , H01L23/28 , H01L23/296 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5226 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/02371 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48237 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/83101 , H01L2224/83385 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/12042 , H01L2924/14 , H01L2924/15183 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , Y10T29/49155 , H01L2924/0665 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.
摘要翻译：半导体封装包括基板单元，与第一接触焊盘电连接的管芯，以及覆盖第一图案化导电层和管芯的封装体。基板单元包括：（1）第一图案化导电层; （2）暴露第一图案化导电层的一部分以形成第一接触焊盘的第一电介质层; （3）第二图案化导电层; （4）限定从第一图案化导电层延伸到第二图案化导电层的开口的第二介电层，其中第二图案化导电层包括由第二介电层暴露的第二接触焊盘; 和（5）通过开口从第一图案化导电层延伸到第二接触垫的导电柱，每个导电柱填充相应的一个开口。导电柱中的至少一个限定了空腔。

34. 发明申请

US20100320610A1 SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF 有权
标题翻译：具有单金属层的基板的半导体封装及其制造方法
公开(公告)号：US20100320610A1
公开(公告)日：2010-12-23
申请号：US12779818
申请日：2010-05-13
申请人： SHIH-FU HUANG , Yuan-Chang Su , Chia-Cheng Chen , Kuang-Hsiung Chen , Ming-Chiang Lee , Bernd Karl Appelt , Chia-Hsiung Hsieh
发明人： SHIH-FU HUANG , Yuan-Chang Su , Chia-Cheng Chen , Kuang-Hsiung Chen , Ming-Chiang Lee , Bernd Karl Appelt , Chia-Hsiung Hsieh
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/145 , H01L24/16 , H01L24/28 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/13099 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
摘要翻译：半导体封装包括基板，管芯和封装体。基材包括：（a）包含用纤维增强的树脂的芯; （b）延伸穿过所述芯的多个开口; （c）电介质层; 和（d）设置在电介质层和芯之间的单个导电层。单个导电层的下表面的一部分覆盖多个开口以形成多个用于半导体封装外部电连接的第一接触焊盘。单个导电层的上表面的暴露部分形成多个第二接触焊盘。模具电连接到多个第二接触焊盘，并且封装体封装模具。

35. 发明申请

US20090075027A1 MANUFACTURING PROCESS AND STRUCTURE OF A THERMALLY ENHANCED PACKAGE 有权
标题翻译：一种热增强包装的制造工艺和结构
公开(公告)号：US20090075027A1
公开(公告)日：2009-03-19
申请号：US12183398
申请日：2008-07-31
申请人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
发明人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
IPC分类号： B32B3/24 , B32B37/00 , B32B38/04 , B32B15/04 , B32B3/00
CPC分类号： B32B37/226 , B32B38/0004 , B32B2305/076 , B32B2305/342 , B32B2311/00 , B32B2315/085 , B32B2457/00 , H01L21/561 , H01L23/295 , H01L23/3128 , H01L23/4334 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , Y10T156/10 , Y10T156/1052 , Y10T428/24331 , Y10T428/24612 , Y10T428/31678 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
摘要翻译：公开了一种用于热增强包装的制造方法。首先，提供至少包括基板的基板条。接下来，在基板的上表面上设置至少一个芯片，并且芯片与基板电连接。然后，设置预浸料和散热金属层，散热金属层设置在预浸料坯的第一表面上，并且预浸料坯的第二表面面向芯片。最后，预浸料通过层压预浸料和基材覆盖芯片。

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