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31. 发明申请

US20070011441A1 Method and system for data-driven runtime alignment operation 审中-公开
标题翻译：数据驱动运行时对齐操作的方法和系统
公开(公告)号：US20070011441A1
公开(公告)日：2007-01-11
申请号：US11176988
申请日：2005-07-08
申请人： Alexandre Eichenberger , Michael Gschwind , Valentina Salapura , Peng Wu
发明人： Alexandre Eichenberger , Michael Gschwind , Valentina Salapura , Peng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/355 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3824
摘要： A method for processing instructions and data in a processor includes steps of: preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and processing the input stream of data in the same data path in response to a second set of instructions. A common portion of a dataflow is used for preparing the input stream of data for processing in response to a first set of instructions under the control of a dynamic parameter specified by an instruction of the first set of instructions, and for operand data routing based on the instruction specification of a second set of instructions during the processing of the input stream in response to the second set of instructions.
摘要翻译：一种用于在处理器中处理指令和数据的方法，包括以下步骤：响应于指定动态参数的第一组指令，准备用于在数据路径中进行处理的输入数据流; 以及响应于第二组指令来处理相同数据路径中的输入数据流。数据流的公共部分用于在由第一组指令的指令指定的动态参数的控制下响应于第一组指令来准备用于处理的输入数据流，并且基于用于基于响应于第二组指令在输入流的处理期间的第二组指令的指令指定。

32. 发明申请

US20060190614A1 Non-homogeneous multi-processor system with shared memory 失效
公开(公告)号：US20060190614A1
公开(公告)日：2006-08-24
申请号：US11065537
申请日：2005-02-24
申请人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

33. 发明申请

US20060155955A1 SIMD-RISC processor module 审中-公开
标题翻译： SIMD-RISC处理器模块
公开(公告)号：US20060155955A1
公开(公告)日：2006-07-13
申请号：US11032194
申请日：2005-01-10
申请人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
发明人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F15/8007 , G06F13/1663
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

34. 发明申请

US20050251654A1 System and method of execution of register pointer instructions ahead of instruction issue 有权
标题翻译：提前执行寄存器指针指令的系统和方法问题
公开(公告)号：US20050251654A1
公开(公告)日：2005-11-10
申请号：US10828794
申请日：2004-04-21
申请人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/3013 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.
摘要翻译：管道系统和方法包括多个操作阶段。这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

35. 发明申请

US20050114629A1 Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code 有权
标题翻译：以与现有代码兼容的方式扩展具有固定长度指令的处理器中指令位数目的方法和装置
公开(公告)号：US20050114629A1
公开(公告)日：2005-05-26
申请号：US10720585
申请日：2003-11-24
申请人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

36. 发明申请

US20130086563A1 COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
标题翻译：用于加强应用二进制接口（ABI）的编码与解码时间指令优化
公开(公告)号：US20130086563A1
公开(公告)日：2013-04-04
申请号：US13251798
申请日：2011-10-03
申请人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

37. 发明授权

US07752505B2 Method and apparatus for detection of data errors in tag arrays 有权
标题翻译：用于检测标签阵列中的数据错误的方法和装置
公开(公告)号：US07752505B2
公开(公告)日：2010-07-06
申请号：US11854887
申请日：2007-09-13
申请人： Michael Gschwind , Michael M. Tsao
发明人： Michael Gschwind , Michael M. Tsao
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.
摘要翻译：用于检测标签阵列中的错误的方法包括使用索引访问标签阵列，从标签阵列中检索至少一个标签，以及基于预期标签来计算奇偶校验位。

38. 发明申请

US20090077425A1 Method and Apparatus for Detection of Data Errors in Tag Arrays 有权
标题翻译：用于检测标签数组中数据错误的方法和装置
公开(公告)号：US20090077425A1
公开(公告)日：2009-03-19
申请号：US11854887
申请日：2007-09-13
申请人： Michael Gschwind , Michael M. Tsao
发明人： Michael Gschwind , Michael M. Tsao
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.
摘要翻译：用于检测标签阵列中的错误的方法包括使用索引访问标签阵列，从标签阵列中检索至少一个标签，以及基于预期标签来计算奇偶校验位。

39. 发明申请

US20080307209A1 METHODS AND APPARATUS FOR IMPLEMENTING POLYMORPHIC BRANCH PREDICTORS 审中-公开
标题翻译：实施多分支预测的方法和装置
公开(公告)号：US20080307209A1
公开(公告)日：2008-12-11
申请号：US12194145
申请日：2008-08-19
申请人： Michael Gschwind
发明人： Michael Gschwind
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3806
摘要： A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to select one or more of the branch prediction methods in accordance with a dynamic setting to optimize performance of the branch predictor during operation in accordance with a current task.
摘要翻译：多态分支预测器和方法包括多个分支预测方法。选择性地启用这些方法来执行分支预测。选择机构被配置为根据动态设置选择一个或多个分支预测方法，以根据当前任务在运行期间优化分支预测器的性能。

40. 发明申请

US20070186077A1 System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism 审中-公开
标题翻译：使用优选插槽对准机制执行指令的系统和方法
公开(公告)号：US20070186077A1
公开(公告)日：2007-08-09
申请号：US11461554
申请日：2006-08-01
申请人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
发明人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.
摘要翻译：提出了一种利用优选槽对准机构执行指令的系统和方法。处理器架构使用向量寄存器文件，共享数据路径和指令执行逻辑来处理单指令多数据（SIMD）指令和标量指令。处理器架构将向量分成四个“时隙”，每个“插槽”包括四个字节，并将标量数据定位在“首选插槽”中，以确保正确定位。使用首选插槽机制的指令包括1）移动和旋转指定移位量的整个四字的操作指令，2）需要地址的存储器加载和存储指令，以及3）使用首选插槽进行分支的分支指令条件（条件分支）和分支地址（寄存器 - 间接分支）。因此，处理器架构消除了单独的问题槽，独立的管道和单独标量单元的控制复杂性的要求。

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