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31. 发明申请

US20180351072A1 DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECTS 审中-公开
公开(公告)号：US20180351072A1
公开(公告)日：2018-12-06
申请号：US15612326
申请日：2017-06-02
申请人： CHRISTOPHER F. KIRBY , VIVIEN M. LUU , MICHAEL RENNIE , SEAN R. MCLAUGHLIN
发明人： CHRISTOPHER F. KIRBY , VIVIEN M. LUU , MICHAEL RENNIE , SEAN R. MCLAUGHLIN
IPC分类号： H01L39/24 , H01L21/768 , H01L21/02 , H01L23/522 , H01L23/532
摘要： A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.

32. 发明申请

US20180138389A1 METHOD OF MAKING A SUPERCONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180138389A1
公开(公告)日：2018-05-17
申请号：US15351755
申请日：2016-11-15
申请人： CHRISTOPHER F. KIRBY , MICHAEL RENNIE , DANIEL J. O'DONNELL
发明人： CHRISTOPHER F. KIRBY , MICHAEL RENNIE , DANIEL J. O'DONNELL
IPC分类号： H01L39/24 , H01L39/12 , H01L39/02
CPC分类号： H01L39/2493 , H01L39/025 , H01L39/12 , H01L39/2406
摘要： A method of forming a superconductor device structure is disclosed. The method comprises forming a base electrode in a first dielectric layer, forming a junction material stack over the base electrode, forming a hardmask over the junction material stack, etching away a portion of the junction material stack to form a Josephson junction (JJ) over the base electrode, and depositing a second dielectric layer over the hardmask, the JJ, the base electrode and the first dielectric layer. The method additionally comprises forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and forming a second contact through the second dielectric layer and the hardmask to electrically coupled the second contact to a second end of the JJ.

33. 发明授权

US09812445B2 Bipolar junction transistor device having base epitaxy region on etched opening in DARC layer 有权
公开(公告)号：US09812445B2
公开(公告)日：2017-11-07
申请号：US14829487
申请日：2015-08-18
申请人： Patrick B. Shea , Michael Rennie , Sandro J. Di Giacomo
发明人： Patrick B. Shea , Michael Rennie , Sandro J. Di Giacomo
IPC分类号： H01L27/07 , H01L29/10 , H01L29/08 , H01L29/737 , H01L29/66 , H01L27/06 , H01L21/8249
CPC分类号： H01L27/0711 , H01L21/02532 , H01L21/02595 , H01L21/31144 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/092 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/737 , H01L29/7371 , H01L29/7378
摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

34. 发明申请

US20170309618A9 BIPOLAR JUNCTION TRANSISTOR DEVICE HAVING BASE EPITAXY REGION ON ETCHED OPENING IN DARC LAYER 有权
公开(公告)号：US20170309618A9
公开(公告)日：2017-10-26
申请号：US14829487
申请日：2015-08-18
申请人： PATRICK B. SHEA , Michael Rennie , Sandro J. Di Giacomo
发明人： PATRICK B. SHEA , Michael Rennie , Sandro J. Di Giacomo
IPC分类号： H01L27/07 , H01L29/737 , H01L29/66 , H01L29/08 , H01L29/10 , H01L27/06 , H01L21/8249
CPC分类号： H01L27/0711 , H01L21/02532 , H01L21/02595 , H01L21/31144 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/092 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/737 , H01L29/7371 , H01L29/7378
摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

35. 发明申请

US20060084222A1 Process for fabricating a semiconductor device having deep trench structures 有权
标题翻译：制造具有深沟槽结构的半导体器件的工艺
公开(公告)号：US20060084222A1
公开(公告)日：2006-04-20
申请号：US10967465
申请日：2004-10-18
申请人： Michael Rennie , Stephen Rusinko
发明人： Michael Rennie , Stephen Rusinko
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer is deposited over the inner surface of the trench in the semiconductor substrate and the upper layer is selectively formed on a principal surface of the semiconductor substrate. During formation of the upper layer, a wall surface is formed in the upper layer that is continuous with the wall surface of the trench in the semiconductor substrate. By forming a second portion of the trench in the selectively-formed upper layer, a deep trench is produced having a high aspect ratio and well defined geometric characteristics.
摘要翻译：用于制造具有深沟槽结构的半导体器件的工艺包括在半导体衬底中形成沟槽的第一部分和在选择性形成的上层中形成沟槽的第二部分。在蚀刻衬底以形成沟槽的第一部分之后，在半导体衬底中的沟槽的内表面上沉积保护层，并且上层选择性地形成在半导体衬底的主表面上。在形成上层期间，在与半导体衬底中的沟槽的壁表面连续的上层中形成壁表面。通过在选择性形成的上层中形成沟槽的第二部分，产生具有高纵横比和明确定义的几何特征的深沟槽。

36. 发明申请

US20180053689A1 PRECLEAN METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION 审中-公开
公开(公告)号：US20180053689A1
公开(公告)日：2018-02-22
申请号：US15238394
申请日：2016-08-16
申请人： CHRISTOPHER F. KIRBY , SANDRO J. DI GIACOMO , MICHAEL RENNIE
发明人： CHRISTOPHER F. KIRBY , SANDRO J. DI GIACOMO , MICHAEL RENNIE
IPC分类号： H01L21/768 , H01L23/532 , H01L39/24
CPC分类号： H01L21/76891 , H01L21/02074 , H01L21/76883 , H01L23/53285
摘要： A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.

37. 发明授权

US09780285B1 Superconductor device interconnect structure 有权
公开(公告)号：US09780285B1
公开(公告)日：2017-10-03
申请号：US15238375
申请日：2016-08-16
申请人： Christopher F. Kirby , Michael Rennie , Daniel J. O'Donnell
发明人： Christopher F. Kirby , Michael Rennie , Daniel J. O'Donnell
IPC分类号： H01L29/06 , H01L29/08 , H01L39/22 , H01L39/02 , H01L39/24
CPC分类号： H01L39/223 , H01L39/025 , H01L39/2493
摘要： A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a base electrode in the first dielectric layer with the base electrode having a top surface aligned with the top surface of the first dielectric layer. The method further comprises forming a Josephson junction (JJ) over the base electrode, depositing a second dielectric layer over the JJ, the base electrode and the first dielectric layer, and forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and a second contact through the second dielectric layer to a second end of the JJ.

38. 发明申请

US20150162322A1 BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME 有权
标题翻译：双极接头晶体管器件及其制造方法
公开(公告)号：US20150162322A1
公开(公告)日：2015-06-11
申请号：US14098199
申请日：2013-12-05
申请人： PATRICK B. SHEA , MICHAEL RENNIE , SANDRO J. DI GIACOMO
发明人： PATRICK B. SHEA , MICHAEL RENNIE , SANDRO J. DI GIACOMO
IPC分类号： H01L27/06 , H01L29/737 , H01L21/265 , H01L29/165 , H01L21/02 , H01L21/306 , H01L27/092 , H01L29/66
CPC分类号： H01L27/0711 , H01L21/02532 , H01L21/02595 , H01L21/31144 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/092 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/737 , H01L29/7371 , H01L29/7378
摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.
摘要翻译：提供了形成双极晶体管器件的方法。该方法包括在集电极有源区域上的衬底上沉积集电极电介质层，在集电极电介质层上沉积电介质抗反射（DARC）层，干蚀刻掉DARC层中的基底开口，并湿法蚀刻掉部分的基底开口中的集电极介电层，以提供到基板的延伸的基部开口。该方法还包括进行基底沉积以在延伸的基底开口中形成基底外延区域，并且延伸在DARC层的第一和第二部分上，该DARC层由于干蚀刻而残留在DARC层中的基底开口处，并形成在基底外延区域上的发射极区域。

39. 发明申请

US20130075862A1 EMBEDDED CAPACITOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：嵌入式电容器及其制造方法
公开(公告)号：US20130075862A1
公开(公告)日：2013-03-28
申请号：US13240748
申请日：2011-09-22
申请人： Michael Rennie , Thomas J. Knight
发明人： Michael Rennie , Thomas J. Knight
IPC分类号： H01L21/20 , H01L29/92
CPC分类号： H01L28/90 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.
摘要翻译：提供了形成电容器的方法。在一个实施例中，一种方法包括在衬底上提供绝缘体材料层，在绝缘体材料层中蚀刻至少一个通孔，并且在至少一个通孔中沉积接触材料填充物以形成第一组触点。该方法还包括：蚀刻与第一组触点的至少一个触点相邻的绝缘体材料层，以形成至少一个空隙，在至少一个空隙上并在第一组触点上沉积介电材料层，并沉积触点材料填写至少空格以形成第二组联系人。

40. 发明申请

US20060084274A1 Edge protection process for semiconductor device fabrication 有权
标题翻译：半导体器件制造的边缘保护工艺
公开(公告)号：US20060084274A1
公开(公告)日：2006-04-20
申请号：US10967869
申请日：2004-10-18
申请人： Michael Rennie , Jon Davis , Robert Fuller , Franz Hagl
发明人： Michael Rennie , Jon Davis , Robert Fuller , Franz Hagl
IPC分类号： H01L21/311
CPC分类号： H01L21/3083 , H01L21/3065
摘要： An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.
摘要翻译：用于半导体器件制造的边缘保护工艺包括在半导体衬底的周缘区域上形成保护层。将半导体衬底放置在等离子体气氛中，并且在衬底中蚀刻诸如深沟槽和浅沟槽隔离结构的沟槽结构。保护层基本上防止了周边边缘区域的蚀刻，使得在蚀刻工艺期间黑色硅的形成基本上被最小化。

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