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31. 发明授权

US06303395B1 Semiconductor processing techniques 失效
标题翻译：半导体处理技术
公开(公告)号：US06303395B1
公开(公告)日：2001-10-16
申请号：US09323601
申请日：1999-06-01
申请人： Jaim Nulman
发明人： Jaim Nulman
IPC分类号： G01R3126
CPC分类号： G05B19/4183 , Y02P80/114 , Y02P90/10 , Y02P90/20 , Y02P90/22 , Y02P90/86 , Y10T29/41
摘要： The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).
摘要翻译：本发明提供了一种用于晶片制造的制造环境（110）和用于设定控制限制并获取生产运行的计量数据的SPC环境（112）。计算环境（114）处理SPC数据，然后在分析环境（116）中对SPC数据进行分析。如果过程超出控制限制，则MES环境（118）评估分析并自动执行过程干预。另外，本发明提供电力管理系统，备件库存和调度系统以及晶片制造效率系统。这些系统采用算法（735,1135和1335）。

32. 发明授权

US06228186B1 Method for manufacturing metal sputtering target for use in DC magnetron so that target has reduced number of conduction anomalies 有权
标题翻译：用于制造用于直流磁控管的金属溅射靶的方法，使得目标具有减少的导通异常的数量
公开(公告)号：US06228186B1
公开(公告)日：2001-05-08
申请号：US09418672
申请日：1999-10-14
申请人： Vikram Pavate , Keith J. Hansen , Glen Mori , Murali Narasimhan , Seshadri Ramaswami , Jaim Nulman
发明人： Vikram Pavate , Keith J. Hansen , Glen Mori , Murali Narasimhan , Seshadri Ramaswami , Jaim Nulman
IPC分类号： C22F100
CPC分类号： C23C14/3414 , Y10S29/002 , Y10S29/005 , Y10T29/49988
摘要： Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.
摘要翻译：公开了用于形成具有低缺陷密度的金属化膜的改进的用于铝或类似金属的DC_磁控溅射的靶。还公开了制造和使用这些靶的方法。诸如由金属氧化物夹杂物组成的电导率异常可以引起目标表面和等离子体之间的电弧。电弧会导致过剩的沉积材料以斑块或斑点的形式产生。减少电导率异常的含量和加强待沉积材料可以减少这种斑块或斑点的产生。其它限制步骤包括平滑地对目标表面进行精加工和等离子体的低应力升高。

33. 发明授权

US5759360A Wafer clean sputtering process 失效
标题翻译：晶圆清洗溅射工艺
公开(公告)号：US5759360A
公开(公告)日：1998-06-02
申请号：US402676
申请日：1995-03-13
申请人： Kenny King-Tai Ngan , Jaim Nulman
发明人： Kenny King-Tai Ngan , Jaim Nulman
IPC分类号： H01L21/302 , B08B7/00 , C23C14/02 , C23C16/02 , H01L21/00 , H01L21/304 , H01L21/306 , H01L21/3065 , C23C14/34
CPC分类号： H01L21/02046 , B08B7/0035 , C23C14/022 , C23C16/0245 , H01L21/67069
摘要： A method of precleaning a silicon wafer to remove a layer of native silicon oxide thereon comprising adding a mixture of argon and oxygen to a plasma etch chamber including a wafer to be cleaned mounted on a cathode in said chamber, while maintaining the pressure in the chamber below about 3 millitorr. The oxygen is added to react with silicon atoms in the plasma but not with silicon atoms of the single crystal silicon wafer. The presence of oxygen in the plasma at low pressure ensures steady plasma generation and uniform etching across the wafer.
摘要翻译：一种预硅化硅晶片以除去其上的天然氧化硅层的方法，其中包括将氩和氧的混合物添加到等离子体蚀刻室中，所述等离子体蚀刻室包括安装在所述室中的阴极上的待清洁晶片，同时保持室内的压力低于约3毫托。添加氧以与等离子体中的硅原子反应，但不与单晶硅晶片的硅原子反应。在低压下在等离子体中存在氧气确保稳定的等离子体产生和跨晶片的均匀蚀刻。

34. 发明授权

US5698989A Film sheet resistance measurement 失效
标题翻译：薄膜电阻测量
公开(公告)号：US5698989A
公开(公告)日：1997-12-16
申请号：US712992
申请日：1996-09-13
申请人： Jaim Nulman
发明人： Jaim Nulman
IPC分类号： G01R27/02 , G01R27/04 , G01R31/26 , H01L21/66 , G01N27/04
CPC分类号： H01L22/20 , B24B37/013 , H01L22/26 , G01R27/04 , G01R31/2648 , H01L22/10
摘要： Apparatus and methods for measuring the sheet resistance of an electrically conductive film on a semiconductor substrate while maintaining the substrate within the vacuum environment of the semiconductor process apparatus. In one aspect of the invention, the conductive film is deposited on the substrate within a vacuum chamber, and the resistance probe is located within the same chamber. The probe retracts out of the way during deposition of the film, and then moves to the substrate to measure the resistance of the film after deposition is paused or completed. In a second aspect of the invention, the probe is located in a chamber other than the chamber which deposits the conductive film. The chamber housing the probe can be the "transfer chamber" which houses the substrate transfer robot used to carry substrates from one process chamber to another, or it can be a cooling chamber which cools the substrate after the film is deposited so that the sheet resistance measurement can be performed at a desired lower temperature. If the probe is located in the transfer chamber, the probe can measure the substrate while it is in the transfer chamber in the course of being transferred from one process chamber to another.
摘要翻译：用于测量半导体衬底上的导电膜的薄层电阻同时将衬底保持在半导体处理装置的真空环境内的装置和方法。在本发明的一个方面，导电膜沉积在真空室内的基片上，电阻探针位于相同的腔室内。探针在沉积薄膜期间缩回，然后移动到基底，以测量沉积暂停或完成后薄膜的电阻。在本发明的第二方面中，探针位于除了沉积导电膜的室之外的室中。容纳探针的腔室可以是容纳用于将衬底从一个处理室运送到另一个处理室的衬底传送机器人的“传送室”，或者可以是在膜沉积之后冷却衬底的冷却室，使得薄层电阻可以在所需的较低温度下进行测量。如果探针位于传送室中，探针可以在从一个处理室转移到另一个处理室的过程中，在传送室内测量衬底。

35. 发明授权

US5443995A Method for metallizing a semiconductor wafer 失效
标题翻译：金属化半导体晶片的方法
公开(公告)号：US5443995A
公开(公告)日：1995-08-22
申请号：US122851
申请日：1993-09-17
申请人： Jaim Nulman
发明人： Jaim Nulman
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76838 , H01L21/76882 , H01L23/53223 , H01L2924/0002 , H01L2924/3011
摘要： A method for metallizing semiconductor materials includes two processing steps. In the first step, a layer of an alloy of conductive metal, such as aluminum, and refractory metal, such as titanium, tungsten or silicon, is deposited on the surface in a single step from a single source. In the second step, a layer of the conductive metal is deposited over the alloy layer. Thus, using this method, metallization can be conveniently performed using two chambers.
摘要翻译：金属化半导体材料的方法包括两个处理步骤。在第一步骤中，一层由诸如铝的导电金属和诸如钛，钨或硅的难熔金属的合金从单个源以一个步骤沉积在表面上。在第二步骤中，在合金层上沉积导电金属层。因此，使用这种方法，可以使用两个室方便地执行金属化。

36. 发明授权

US5360996A Titanium nitride/titanium silicide multiple layer barrier with preferential (111) crystallographic orientation on titanium nitride surface 失效
标题翻译：在氮化钛表面上具有优先（111）晶体取向的氮化钛/硅化钛多层势垒
公开(公告)号：US5360996A
公开(公告)日：1994-11-01
申请号：US65309
申请日：1993-05-21
申请人： Jaim Nulman , Kenny K. Ngan
发明人： Jaim Nulman , Kenny K. Ngan
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/34
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855 , H01L21/76876 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , Y10S438/927 , Y10S438/973
摘要： A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.
摘要翻译：描述了一种在硅表面上形成具有（111）晶体取向表面的氮化钛阻挡层的方法。该方法包括：在硅表面上沉积第一钛层; 在钛层上溅射氮化钛层; 在溅射的氮化钛层上沉积第二钛层; 然后在含氮气体的存在下退火该结构，并且在不存在含氧气体的情况下，形成具有（111）晶体取向表面和足够厚度的所需氮化钛以提供保护底层硅对铝的尖峰。当随后在（111）取向的氮化钛表面上形成铝层时，铝将呈现相同的（111）晶体取向，导致铝层具有增强的电迁移阻力。

37. 发明授权

US5288665A Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures 失效
标题翻译：用于形成低电阻铝插头的方法，电连接到用于集成电路结构的上覆图案化金属层
公开(公告)号：US5288665A
公开(公告)日：1994-02-22
申请号：US928813
申请日：1992-08-12
申请人： Jaim Nulman
发明人： Jaim Nulman
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44 , H01L21/48
CPC分类号： H01L21/32051 , H01L21/76877
摘要： A process is described for forming an aluminum plug in a via in an insulating layer in an integrated circuit structure by first depositing a layer of aluminum over the insulating layer in a multistep deposition which will also result in filling the via with aluminum to form an aluminum plug therein, followed by removal of any additional aluminum formed over the surface of the insulating layer, and subsequent formation of one or more patterned conductive layers over the insulating surface which is in electrical communication with the underlying aluminum plug in the via. The one or more patterned conductive layers formed over the insulating surface are characterized by superior electrical properties over the aluminum layer initially deposited and then removed. A barrier layer may be first formed over exposed portions of the underlying integrated circuit structure at the bottom of the via before it is filled with aluminum.
摘要翻译：描述了一种用于在集成电路结构的绝缘层中在通孔中形成铝插塞的工艺，首先在多步沉积中在绝缘层上沉积铝层，这也将导致用铝填充通孔以形成铝插入其中，随后除去在绝缘层的表面上形成的任何附加的铝，随后在绝缘表面上形成一个或多个图案化的导电层，绝缘表面与通孔中的下面的铝插塞电连通。在绝缘表面上形成的一个或多个图案化导电层的特征在于优先于最初沉积并随后被去除的铝层上的电性能。阻挡层可以先在通孔的底部在其被铝填充之前形成在下面的集成电路结构的暴露部分上。

38. 发明授权

US5236868A Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system 失效
标题翻译：通过在一体化加工系统中与氮气承载气体反应的钛酸钠在半导体陶瓷上形成硝酸钛
公开(公告)号：US5236868A
公开(公告)日：1993-08-17
申请号：US511652
申请日：1990-04-20
申请人： Jaim Nulman
发明人： Jaim Nulman
IPC分类号： C23C16/34 , H01L21/28 , H01L21/285 , H01L21/321
CPC分类号： H01L21/285 , H01L21/3211 , Y10S438/906 , Y10S438/976
摘要： A process is disclosed for forming a layer of titanium nitride on a semiconductor wafer which comprises forming a titanium layer on the wafer in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in the sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400.degree. C. up to below about 650.degree. C. to form a titanium nitride compound on the wafer; and further annealing the wafer at a temperature of from about 800.degree. C. to about 900.degree. C. to form a stable phase of stoichiometric titanium nitride (TiN) on the wafer. The resulting layer of titanium nitride may be patterned to form local interconnects on the wafer, as well as to provide barrier portions between underlying titanium silicide and metal contacts such as aluminum. In a preferred embodiment, the initial annealing temperature ranges from about 400.degree. C. up to below about 600.degree. C. whereby substantially all of the titanium will react with the nitrogen to form titanium nitride on the wafer.

39. 发明授权

US4989991A Emissivity calibration apparatus and method 失效
标题翻译：发射率校准装置及方法
公开(公告)号：US4989991A
公开(公告)日：1991-02-05
申请号：US365678
申请日：1989-06-12
申请人： Michel Pecot , Jaim Nulman
发明人： Michel Pecot , Jaim Nulman
IPC分类号： G01J5/00 , G01J5/04
CPC分类号： G01J5/0003 , G01J5/0007 , G01J5/041 , G01J5/045 , G01J5/524 , G01J2005/0048 , G01J2005/068
摘要： An improved method and apparatus are disclosed for calibrating the emissivity characteristics of a semiconductor wafer within a processing chamber by supporting a sample wafer on a graphite susceptor within the chamber and by comparing the temperature measured within the susceptor in close proximity to the center of the wafer with the temperature measured by the emission of radiation from the surface of the wafer through the walls of the processing chamber. Temperature measurements subsequently made from the radiation emitted from the surface of similar wafers are corrected with reference to the measurement made of the temperature within the susceptor on the sample wafer.
摘要翻译：公开了一种改进的方法和装置，用于通过将样品晶片支撑在腔室内的石墨感受器上来校准处理室内的半导体晶片的发射率特性，并且通过将基座内测量的温度与晶片的中心相接近其温度通过从晶片表面通过处理室的壁的辐射而被测量。随后从相似晶片表面发射的辐射产生的温度测量参照由样品晶片上的基座内的温度进行的测量来校正。

40. 发明授权

US06783639B2 Coils for generating a plasma and for sputtering 有权
公开(公告)号：US06783639B2
公开(公告)日：2004-08-31
申请号：US10052951
申请日：2002-01-17
申请人： Jaim Nulman , Sergio Edelstein , Mani Subramani , Zheng Xu , Howard Grunes , Avi Tepman , John Forster , Praburam Gopalraja
发明人： Jaim Nulman , Sergio Edelstein , Mani Subramani , Zheng Xu , Howard Grunes , Avi Tepman , John Forster , Praburam Gopalraja
IPC分类号： C23C1434
CPC分类号： H01J37/3438 , H01J37/3402
摘要： A sputtering coil for a plasma chamber in a semiconductor fabrication system is provided. The sputtering coil couples energy into a plasma and also provides a source of sputtering material to be sputtered onto a workpiece from the coil to supplement material being sputtered from a target onto the workpiece. Alternatively a plurality of coils may be provided, one primarily for coupling energy into the plasma and the other primarily for providing a supplemental source of sputtering material to be sputtered on the workpiece.

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