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31. 发明申请

US20080101522A1 Programmable Local Clock Buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US20080101522A1
公开(公告)日：2008-05-01
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

32. 发明授权

US07284029B2 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US07284029B2
公开(公告)日：2007-10-16
申请号：US10702989
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

33. 发明授权

US07276932B2 Power-gating cell for virtual power rail control 有权
标题翻译：用于虚拟电源轨控制的电源门控单元
公开(公告)号：US07276932B2
公开(公告)日：2007-10-02
申请号：US10926597
申请日：2004-08-26
申请人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K19/23
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译：虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。控制信号在单元边界被锁存或响应于时钟信号锁存。

34. 发明授权

US06980018B2 Self limiting gate leakage driver 失效
标题翻译：自限制闸极泄漏驱动器
公开(公告)号：US06980018B2
公开(公告)日：2005-12-27
申请号：US10835501
申请日：2004-04-29
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/003 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲区的逻辑功能，无需驱动大负载。第二和第三逻辑路径具有直到最后一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器可以是逆变器，非逆变器，或提供多输入逻辑功能。

35. 发明授权

US06963629B2 Adaptive phase locked loop 有权
标题翻译：自适应锁相环
公开(公告)号：US06963629B2
公开(公告)日：2005-11-08
申请号：US09918809
申请日：2001-07-31
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
IPC分类号： H03D13/00 , H03L7/089 , H03L7/107 , H03D3/24 , H03L7/06
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0898
摘要： A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values. The first gain signal is multiplied by a Pump current increment and added to a minimum Pump current to generate a variable Pump current. A variable second gain signal proportional to the time the reference signal leads and lags the VCO signal multiplies the Pump current. The amplified Pump current is summed with an integral of the amplified Pump current to generate a control signal. The control signal is applied to the VCO and determines the frequency of the VCO output.
摘要翻译：比较参考信号和压控振荡器（VCO）输出的相对相位和频率差。如果参考信号引导VCO输出，则产生引导误差信号，如果参考信号滞后于VCO输出引起滞后误差信号产生滞后误差，则滞后误差可能由参考信号和 VCO输出。时间窗口用于通过递增和递减相位误差信号来对引线和滞后误差信号的极性进行采样。如果相位误差信号在时间窗内达到阈值，则产生复位增量脉冲，如果相位误差信号在时间窗口内未达到最大增量值，则产生复位总脉冲。在每个复位增量脉冲上增加可变的第一增益信号，并在每个复位总脉冲上减小，并限制在预定的最大和最小值之间的值。第一个增益信号乘以泵电流增量，并加到最小泵电流以产生可变泵电流。与参考信号引导和滞后于VCO信号的时间成比例的可变第二增益信号与泵电流相乘。放大的泵电流与放大的泵电流的积分相加以产生控制信号。控制信号被施加到VCO并确定VCO输出的频率。

36. 发明授权

US06529082B1 Dual mode charge pump 失效
标题翻译：双模电荷泵
公开(公告)号：US06529082B1
公开(公告)日：2003-03-04
申请号：US09975187
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03L700
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/107
摘要： A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal. A first bi-directional transfer gate is coupled between the output nodes of the first and third CSs and is controlled by a Mode control signal and a second bi-directional transfer gate is coupled between the output nodes of the second and fourth CSs and is also controlled by the Mode control signal. States of the control signals allow a dual mode where either a first or second current level may be delivered into or out of components coupled to the first and second charge pump nodes.
摘要翻译：电荷泵有两个电荷泵节点。第一电荷泵节点具有源极端子连接到正电源电压的第一电流源（CS）和连接到第一电荷泵节点的输出端子，其中P沟道金属氧化物硅晶体管（PFET）由第一控制信号。第一电荷泵节点还连接到具有连接到接地电源电压的源极端子的第二CS，以及通过第二控制信号控制的NFET连接到第二CS的输出端子。第二电荷泵节点具有连接到正电源电压的源极端子的第三CS和与由第三控制信号控制的PFET连接到第二电荷泵节点的输出端子。第二电荷泵节点还连接到具有连接到接地电源电压的源极端子的第四CS和连接到具有由第四控制信号控制的NFET的第二CS的输出端子。第一双向传输门耦合在第一和第三CS的输出节点之间，并且由模式控制信号控制，第二双向传输门耦合在第二和第四CS的输出节点之间，并且也是由模式控制信号控制。控制信号的状态允许双模式，其中第一或第二电流电平可以被传送到耦合到第一和第二电荷泵节点的组件中或从耦合到第一和第二电荷泵节点的组件中。

37. 发明授权

US06515530B1 Dynamically scalable low voltage clock generation system 有权
标题翻译：动态可升级的低压时钟发生系统
公开(公告)号：US06515530B1
公开(公告)日：2003-02-04
申请号：US09974985
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F104
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock. If any of the scaling dynamics may affect the system clock, then the fixed frequency clock may be selected as the system clock until any transients have stabilized. The MUX may also stop the system in a known logic state. The PLL may also be optimized while the system is running.
摘要翻译：锁相环（PLL）电路使用可编程分频器（PRFD）从PLL输出时钟产生反馈时钟。通过在调节器电路中调节系统的可伸缩逻辑电源电压来产生PLL电源电压和PLL参考电流。 PLL电源电压调节到低于系统使用的可伸缩逻辑电源电压的最低电平。 PLL产生PLL输出时钟，其频率高于使用最高级别的可伸缩逻辑电源电压的系统的最高工作频率。 PLL输出时钟分为第二个PRFD，用于产生一个分频的PLL时钟。在无毛刺多路复用器（MUX）中选择PLL时钟和固定辅助时钟作为系统的系统时钟。可以通过在分频PLL时钟的第二PRFD中对除数进行编程来动态地缩放系统时钟频率。如果任何缩放动力学可能影响系统时钟，则可以选择固定频率时钟作为系统时钟，直到任何瞬变稳定为止。 MUX还可以以已知的逻辑状态停止系统。 PLL也可以在系统运行时进行优化。

38. 发明授权

US06501304B1 Glitch-less clock selector 失效
标题翻译：无毛刺时钟选择器
公开(公告)号：US06501304B1
公开(公告)日：2002-12-31
申请号：US09974990
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K1700
CPC分类号： G06F1/08
摘要： A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare. The new clock signal (MUX output) latches the compare signal and again enables the clock output signal when the new clock signal transitions from a one to a zero. The clock output signal now transitions to a logic one on the next positive transition of the new clock signal guaranteeing glitch free operation. In another embodiment more than two clock signals are selected by providing a multi-bit select signal and registers instead of single bit latches. The select signal is decoded to provide the select signal for the MUX which now selects between more than two clock signals.
摘要翻译：无干扰时钟选择器在异步时钟信号之间进行选择。在一个实施例中，选择信号具有对应于两个时钟信号的两个逻辑状态。时钟输出信号通过锁存的比较信号选通，该比较信号将新的选择信号状态与存储的当前选择信号状态进行比较。多路复用器（MUX）响应于选择锁存器输出信号在两个时钟信号之间进行选择。如果新的和当前的选择信号不比较，当MUX输出（当前选定的时钟信号）变为逻辑0时，通过比较锁存器的输出将时钟输出信号强制为逻辑0，该比较锁存器锁存比较信号。当本时钟信号保持低电平时，MUX切换到新的时钟信号。新的时钟信号（MUX输出）将新的选择状态锁定为当前选择状态，导致新的和当前的选择信号进行比较。新的时钟信号（MUX输出）锁存比较信号，并且当新的时钟信号从一个转换到零时，再次启用时钟输出信号。时钟输出信号现在在保证无毛刺操作的新时钟信号的下一个正转换时转变为逻辑1。在另一个实施例中，通过提供多位选择信号来选择两个以上的时钟信号，并且寄存器而不是单个位锁存器。选择信号被解码以提供现在在两个以上的时钟信号之间选择的MUX的选择信号。

39. 发明授权

US5881274A Method and apparatus for performing add and rotate as a single instruction within a processor 失效
标题翻译：用于在处理器内作为单个指令执行加法和旋转的方法和装置
公开(公告)号：US5881274A
公开(公告)日：1999-03-09
申请号：US900261
申请日：1997-07-25
申请人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
发明人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
IPC分类号： G06F9/302 , G06F9/315 , G06F9/305
CPC分类号： G06F9/3001 , G06F9/30032
摘要： An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.
摘要翻译：公开了一种用于在处理器内执行ADD和ROTATE作为单个指令的装置。根据本发明的优选实施例，该装置包括加法器和旋转器。加法器用于将多个第一数字加到多个第二数目中以产生一个进位输出和一个和输出。在每个阶段中，加法器产生组生成值和组传播值。旋转器用于旋转组传播值，并且在进位输出和总和输出的屈服之前的组中的每个级产生组生成值。因此，ADD和ROTATE指令都可以在单个处理器周期内完成。

40. 发明授权

US5627774A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5627774A
公开(公告)日：1997-05-06
申请号：US473308
申请日：1995-06-07
申请人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
发明人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

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