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31. 再颁专利

USRE43674E1 Post passivation metal scheme for high-performance integrated circuit devices 有权
标题翻译：后钝化金属方案用于高性能集成电路器件
公开(公告)号：USRE43674E1
公开(公告)日：2012-09-18
申请号：US11518595
申请日：2006-09-08
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.
摘要翻译：在已经被常规钝化层覆盖的IC器件的表面上提供了新的后钝化金属互连方案。本发明的金属方案包括叠加常规的钝化层，厚和宽的金属线与厚的介电层和接合焊盘的组合。本发明的互连系统可以用于将功率，接地，信号和时钟线从接合焊盘分配到设置在IC器件的任何位置的器件的电路，而不引入显着的功率下降。由于低阻抗钝化后互连，不需要或更小的ESD电路，因为任何累积的静电放电将均匀分布在芯片上电路的所有结电容上。后钝化金属方案通过接合焊盘，焊接，TAB接合等连接到外部电路。互连金属方案的顶层使用用于引线键合的复合金属形成，复合金属在体导电金属上形成。扩散金属可以施加在本体金属和复合金属之间，另外在体导电金属之下可能需要一层下阻挡金属（UBM）。

32. 发明授权

US08178967B2 Low fabrication cost, high performance, high reliability chip scale package 有权
标题翻译：低制造成本，高性能，高可靠性芯片级封装
公开(公告)号：US08178967B2
公开(公告)日：2012-05-15
申请号：US11930210
申请日：2007-10-31
申请人： Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/525 , H01L24/11 , H01L24/16 , H01L24/48 , H01L2224/0231 , H01L2224/02311 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13023 , H01L2224/131 , H01L2224/45099 , H01L2224/48227 , H01L2224/73203 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H05K3/108 , H05K3/243 , H05K3/3473 , H05K2201/0367 , H05K2201/09436 , H05K2201/0949 , H05K2203/043 , H05K2203/054 , H01L2224/13099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
摘要翻译：本发明提供了一种新的方法和芯片级封装。本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从接触垫电镀/种子层的暴露表面被电镀以产生互连迹线。从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

33. 发明申请

US20110309473A1 CHIP PACKAGE WITH DIE AND SUBSTRATE 有权
标题翻译：带芯片和基板的芯片包装
公开(公告)号：US20110309473A1
公开(公告)日：2011-12-22
申请号：US13159190
申请日：2011-06-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/498
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
摘要翻译：使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

34. 发明申请

US20110291259A9 Reliable metal bumps on top of I/O pads after removal of test probe marks 有权
标题翻译：移除测试探针后，I / O焊盘顶部可靠的金属凸块
公开(公告)号：US20110291259A9
公开(公告)日：2011-12-01
申请号：US12182145
申请日：2008-07-30
申请人： Ching-Cheng Huang , Chuen-Jye Lin , Ming-Ta Lei , Mou-Shiung Lin
发明人： Ching-Cheng Huang , Chuen-Jye Lin , Ming-Ta Lei , Mou-Shiung Lin
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/02166 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05018 , H01L2224/05019 , H01L2224/05027 , H01L2224/05093 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05562 , H01L2224/05572 , H01L2224/1147 , H01L2224/11901 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012
摘要： In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
摘要翻译：根据本发明的目的，提供了一种在I / O焊盘的表面上形成金属凸块的新方法。接触垫设置在电介质层的表面上。在晶片级半导体器件测试期间用作I / O焊盘的I / O焊盘的铝在使用金属干燥的方法的表面积小于接触焊盘的表面积的情况下被完全或部分地去除蚀刻或湿蚀刻。接触焊盘可以通过在接触焊盘的平面中产生的互连金属或通过已经沉积接触焊盘的电介质层提供的通孔来访问。通过在用于保护接触焊盘的钝化层上的聚酰亚胺层的沉积，图案化和蚀刻可以进一步扩展该工艺。

35. 发明授权

US07906849B2 Chip structure and process for forming the same 有权
公开(公告)号：US07906849B2
公开(公告)日：2011-03-15
申请号：US12032707
申请日：2008-02-18
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/10 , H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0251 , H01L27/0676 , H01L27/08 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , Y10T29/49124 , Y10T29/49204 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

36. 发明申请

US20100087659A1 NORBORNENE COMPOUNDS WITH CROSS-LINKABLE GROUPS AND THEIR DERIVATIVES 有权
标题翻译：具有可交联组合的诺贝恩化合物及其衍生物
公开(公告)号：US20100087659A1
公开(公告)日：2010-04-08
申请号：US12555448
申请日：2009-09-08
申请人： Der-Jang Liaw , Ching-Cheng Huang , Shou-Mau Hong , Ming-Hung Huang
发明人： Der-Jang Liaw , Ching-Cheng Huang , Shou-Mau Hong , Ming-Hung Huang
IPC分类号： C07D303/12 , C07D209/34
CPC分类号： C08F232/08
摘要： The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction index and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance.
摘要翻译：本发明提供了具有可交联基团的降冰片烯化合物及其衍生聚合物，其中所述可交联基团是烯烃或环氧基团。通过活性开环复分解法制备具有可交联侧链的降冰片烯聚合物及其嵌段共聚物以及改性衍生物。所得聚合物具有优异的溶解度和光学性能，分子量分布窄，分子量控制小，折射率小，透明度高。它们也适用于制备具有高热稳定性和耐化学性的混合材料。

37. 发明申请

US20090011542A1 Structure and manufactruing method of chip scale package 有权
公开(公告)号：US20090011542A1
公开(公告)日：2009-01-08
申请号：US12206754
申请日：2008-09-09
申请人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
IPC分类号： H01L21/50
CPC分类号： H01L23/293 , H01L23/3114 , H01L23/49827 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05155 , H01L2224/05599 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

38. 发明申请

US20080188071A1 Low fabrication cost, fine pitch and high reliability solder bump 审中-公开
公开(公告)号：US20080188071A1
公开(公告)日：2008-08-07
申请号：US12098469
申请日：2008-04-07
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L24/02 , H01L24/05 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13007 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

39. 发明授权

US07397117B2 Chip package with die and substrate 有权
标题翻译：芯片封装，带芯片和基板
公开(公告)号：US07397117B2
公开(公告)日：2008-07-08
申请号：US10996535
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/053 , H01L21/44
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
摘要翻译：使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

40. 发明申请

US20080146019A1 Chip structure and process for forming the same 有权
公开(公告)号：US20080146019A1
公开(公告)日：2008-06-19
申请号：US12025000
申请日：2008-02-02
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0248 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05073 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

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