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31. 发明授权

US07470988B2 Chip structure and process for forming the same 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US07470988B2
公开(公告)日：2008-12-30
申请号：US10997145
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/10 , H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0251 , H01L27/0676 , H01L27/08 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , Y10T29/49124 , Y10T29/49204 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

32. 发明申请

US20080142978A1 Chip structure and process for forming the same 有权
公开(公告)号：US20080142978A1
公开(公告)日：2008-06-19
申请号：US12024998
申请日：2008-02-02
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0248 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05073 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

33. 发明申请

US20080113503A1 LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE 有权
公开(公告)号：US20080113503A1
公开(公告)日：2008-05-15
申请号：US11930220
申请日：2007-10-31
申请人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L21/441
CPC分类号： H04B1/7113 , H01L21/563 , H01L23/3114 , H01L23/3128 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/15 , H01L24/16 , H01L24/17 , H01L2224/0231 , H01L2224/0401 , H01L2224/1147 , H01L2224/11831 , H01L2224/11901 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H01L2224/13099 , H01L2924/00
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

34. 发明申请

US20080054459A1 Low fabrication cost, fine pitch and high reliability solder bump 审中-公开
公开(公告)号：US20080054459A1
公开(公告)日：2008-03-06
申请号：US11930156
申请日：2007-10-31
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L24/02 , H01L24/05 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13007 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

35. 发明授权

US07338890B2 Low fabrication cost, high performance, high reliability chip scale package 有权
公开(公告)号：US07338890B2
公开(公告)日：2008-03-04
申请号：US11136650
申请日：2005-05-24
申请人： Jin Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/525 , H01L24/11 , H01L24/16 , H01L24/48 , H01L2224/0231 , H01L2224/02311 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13023 , H01L2224/131 , H01L2224/45099 , H01L2224/48227 , H01L2224/73203 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H05K3/108 , H05K3/243 , H05K3/3473 , H05K2201/0367 , H05K2201/09436 , H05K2201/0949 , H05K2203/043 , H05K2203/054 , H01L2224/13099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

36. 发明申请

US20050189650A1 Low fabrication cost, high performance, high reliability chip scale package 有权
公开(公告)号：US20050189650A1
公开(公告)日：2005-09-01
申请号：US11120234
申请日：2005-05-02
申请人： Jin Lee , Ming Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin Lee , Ming Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L21/44 , H01L21/56 , H01L21/60 , H01L23/31 , H01L23/485 , H01L23/525 , H04B1/707 , H04B7/26 , H05K3/10 , H05K3/24 , H05K3/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/525 , H01L24/11 , H01L24/16 , H01L24/48 , H01L2224/0231 , H01L2224/02311 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13023 , H01L2224/131 , H01L2224/45099 , H01L2224/48227 , H01L2224/73203 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H05K3/108 , H05K3/243 , H05K3/3473 , H05K2201/0367 , H05K2201/09436 , H05K2201/0949 , H05K2203/043 , H05K2203/054 , H01L2224/13099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

37. 发明申请

US20050093113A1 Thin film semiconductor package and method of fabrication 有权
公开(公告)号：US20050093113A1
公开(公告)日：2005-05-05
申请号：US10996535
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L21/60 , H01L21/68 , H01L23/31 , H01L23/538 , H01L23/58
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

38. 发明授权

US06700162B2 Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip 有权
标题翻译：芯片结构提高电阻电容延迟并减少芯片的能量损耗
公开(公告)号：US06700162B2
公开(公告)日：2004-03-02
申请号：US10337673
申请日：2003-01-06
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L2348
CPC分类号： H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/45 , H01L27/0676 , H01L27/08 , H01L28/10 , H01L28/20 , H01L2221/1036 , H01L2224/0401 , H01L2224/16 , H01L2224/45 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15174 , H01L2924/19041 , H01L2924/19051 , H01L2924/30105 , H01L2924/3011 , H01L2224/48 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

39. 发明授权

US06673698B1 Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers 有权
标题翻译：利用具有复合聚合物/金属互连层的玻璃基板的薄膜半导体封装
公开(公告)号：US06673698B1
公开(公告)日：2004-01-06
申请号：US10054001
申请日：2002-01-19
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L2146
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
摘要翻译：使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

40. 发明公开

US20240093668A1 TURBINE DEVICE, POWER APPARATUS AND POWER INTEGRATED SYSTEM OF ELECTRIC POWER SYSTEM 审中-公开
公开(公告)号：US20240093668A1
公开(公告)日：2024-03-21
申请号：US18467744
申请日：2023-09-15
申请人： Ching-Cheng HUANG
发明人： Ching-Cheng HUANG , Chien-Jui HUANG
IPC分类号： F03D3/06 , F03B3/14 , F03D3/00 , F03D3/04 , F03D15/00
CPC分类号： F03D3/067 , F03B3/14 , F03D3/005 , F03D3/0436 , F03D15/201 , F05B2240/13 , F05B2240/217 , F05B2240/37 , F05B2260/4022
摘要： A turbine of a power generating system includes a rotary shaft, blades, stoppers and elastic members. Each of the blades includes a connecting side and an active side opposite to the connecting side, and the blades are disposed on the rotary shaft at intervals by a predetermined distance, in which the blades are pivotally connected to the rotary shaft through the connecting sides. The stoppers respectively correspond to the blades and are disposed over the rotary shaft for limiting expansion angles of the blades. Each of the elastic members includes a fixed end and a moving end opposite to the fixed end, and the fixed ends attach to the rotary shaft, and the moving ends respectively attach to the blades. Each of the blades pivots between an expanded position and a closed position.

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