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31. 发明申请

US20120126840A1 Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment 审中-公开
标题翻译：具有十字形碰撞的半导体器件和测试焊盘对准
公开(公告)号：US20120126840A1
公开(公告)日：2012-05-24
申请号：US13240738
申请日：2011-09-22
申请人： Dong-Hyuk Lee , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Chi-Sung Oh
IPC分类号： G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0346 , H01L2224/0362 , H01L2224/0401 , H01L2224/0557 , H01L2224/1146 , H01L2224/11622 , H01L2224/13005 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14136 , H01L2224/16146 , H01L2224/16225 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes.
摘要翻译：半导体器件包括半导体衬底; 沿着半导体衬底的第一轴线方向设置成多行的凸块; 以及沿着垂直于第一轴线方向的第二轴线方向设置在一个或多个列中的测试焊盘。凸块和测试焊盘在半导体衬底的中心部分形成十字形。在半导体衬底的中心部分设置凸起有助于在半导体堆叠的堆叠半导体器件之间形成物理连接，而与芯片尺寸无关。

32. 发明申请

US20110249483A1 STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE 有权
标题翻译：具有片间连接单元的堆叠存储器件，包括其的存储器系统以及传输线延迟时间补偿方法
公开(公告)号：US20110249483A1
公开(公告)日：2011-10-13
申请号：US13080061
申请日：2011-04-05
申请人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
发明人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/10 , G11C5/02 , G11C7/1048
摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
摘要翻译：提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号传输线。层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

33. 发明申请

US20100177576A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100177576A1
公开(公告)日：2010-07-15
申请号：US12686561
申请日：2010-01-13
申请人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
发明人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
IPC分类号： G11C7/08
CPC分类号： G11C7/065 , G11C5/025 , G11C7/08 , G11C11/4091
摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.
摘要翻译：半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器响应于第二读出放大器控制信号的驱动信号。控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

34. 发明申请

US20090059711A1 Routing access with minimized bus area in multi-port memory device 失效
标题翻译：多端口存储设备中路由访问最小化总线面积
公开(公告)号：US20090059711A1
公开(公告)日：2009-03-05
申请号：US11977101
申请日：2007-10-23
申请人： Chi-Sung Oh , Jung-Sik Kim
发明人： Chi-Sung Oh , Jung-Sik Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1075
摘要： A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.
摘要翻译：多端口存储器设备包括第一和第二端口，分配给第一端口的第一专用存储器区域，具有由第一和第二端口共享访问的多个共享存储器单元，用于第一端口的第一组I / O线专用存储器区域和用于共享存储器单元的第二组I / O线，其中第二组具有比第一组更多的I / O线。例如，第二组具有比第一组多N个I / O线，其中N是多端口存储器件的端口数，或者N是共享存储器区域中的多个共享存储体。

35. 发明授权

US07394711B2 Multi-port semiconductor memory device and method for accessing and refreshing the same 失效
标题翻译：多端口半导体存储器件及其访问和刷新方法
公开(公告)号：US07394711B2
公开(公告)日：2008-07-01
申请号：US11616846
申请日：2006-12-27
申请人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
发明人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1075 , G11C8/10 , G11C8/12 , G11C11/40603 , G11C11/40618
摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.
摘要翻译：提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

36. 发明申请

US20140223257A1 SEMICONDUCOTR MEMORY DEVICE INCLUDING NON-VOLATILE MEMORY CELL ARRAY 有权
标题翻译：包括非易失性存储器单元阵列的SEMICONDUCOTR存储器件
公开(公告)号：US20140223257A1
公开(公告)日：2014-08-07
申请号：US14165820
申请日：2014-01-28
申请人： Chi-Sung OH , Chul-Sung PARK , Sang-Bo LEE , Dong-Hyun SOHN
发明人： Chi-Sung OH , Chul-Sung PARK , Sang-Bo LEE , Dong-Hyun SOHN
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/16 , G11C11/005 , G11C11/40 , G11C11/4076 , G11C29/42 , G11C29/4401 , G11C29/785 , G11C2029/0409 , G11C2029/0411 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.
摘要翻译：公开了可以使用纠错电路校正错误数据的半导体存储器件。半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

37. 发明申请

US20110007576A1 SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY SEMICONDUCTOR DEVICE FOR CONTROLLING OUTPUT DATA 有权
标题翻译：用于控制输出数据的同步动态随机存取存储器半导体器件
公开(公告)号：US20110007576A1
公开(公告)日：2011-01-13
申请号：US12702809
申请日：2010-02-09
申请人： Sang-kyu Kang , Ho-cheol Lee , Chi-sung Oh
发明人： Sang-kyu Kang , Ho-cheol Lee , Chi-sung Oh
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.
摘要翻译：提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。每个输出缓冲器都配置为输出一位数据。选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。

38. 发明申请

US20070150669A1 MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING PORT STATE SIGNALING FUNCTION 有权
标题翻译：具有端口状态信号功能的多通道可访问半导体存储器件
公开(公告)号：US20070150669A1
公开(公告)日：2007-06-28
申请号：US11466399
申请日：2006-08-22
申请人： Hyo-Joo AHN , Chi-Sung OH
发明人： Hyo-Joo AHN , Chi-Sung OH
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1048 , G11C8/16 , G11C2207/105 , G11C2207/108
摘要： A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.
摘要翻译：提供了一种具有可由多个处理器随机访问的DRAM存储单元阵列中的共享存储区的多路径可访问半导体存储器件。多路径可访问半导体存储器件包括分配在存储单元阵列中的至少一个共享存储器区域，可操作地连接到对应于多个处理器的端口，由相应处理器使用的每个端口选择性地访问共享存储器区域。该设备还包括占用状态信令单元，用于向处理器输出端口占用状态信息，请求通过用于访问请求的端口访问共享存储器区域，以指示是否允许对共享存储器区域的访问。

39. 发明授权

US06724242B2 Pump circuits and methods for integrated circuits including first and second oscillators and first and second pumps 有权
标题翻译：包括第一和第二振荡器以及第一和第二泵的集成电路的泵电路和方法
公开(公告)号：US06724242B2
公开(公告)日：2004-04-20
申请号：US10370398
申请日：2003-02-20
申请人： Hyung-Dong Kim , Chi-Sung Oh
发明人： Hyung-Dong Kim , Chi-Sung Oh
IPC分类号： G05F302
CPC分类号： H02M3/073 , H02M2001/0032 , H02M2003/077 , Y02B70/16
摘要： Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.
摘要翻译：升压电压产生，并且集成电路的方法被配置为响应于检测到初始电压的下降而将初始升压电压升压到第一升压电压。然后响应于脉冲将第一升压电压升压到第二升压电压。然后响应于振荡信号，第二升压电压被反复升高以接近初始升压电压。因此，可能产生稳定的升压电压。

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