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31. 发明授权

US07618864B2 Nonvolatile memory device and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US07618864B2
公开(公告)日：2009-11-17
申请号：US11589178
申请日：2006-10-30
申请人： Chang-woo Oh , Sung-hwan Kim , Dong-gun Park , Dong-won Kim
发明人： Chang-woo Oh , Sung-hwan Kim , Dong-gun Park , Dong-won Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42324 , H01L29/42332 , H01L29/7887
摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.
摘要翻译：示例性实施例涉及半导体存储器件及其形成方法。其他示例实施例涉及非易失性存储器件及其形成方法。存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。

32. 发明申请

US20090203178A1 Memory device and method of manufacturing the same 有权
公开(公告)号：US20090203178A1
公开(公告)日：2009-08-13
申请号：US12385496
申请日：2009-04-09
申请人： Na-Young Kim , Chang-Woo Oh , Sung-Hwan Kim , Yong-Lack Choi
发明人： Na-Young Kim , Chang-Woo Oh , Sung-Hwan Kim , Yong-Lack Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/78648 , H01L29/7923
摘要： A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.

33. 发明申请

US20080099811A1 SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法
公开(公告)号：US20080099811A1
公开(公告)日：2008-05-01
申请号：US11829113
申请日：2007-07-27
申请人： Nam-Kyun TAK , Ki-Whan SONG , Chang-Woo OH , Woo-Yeong CHO
发明人： Nam-Kyun TAK , Ki-Whan SONG , Chang-Woo OH , Woo-Yeong CHO
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/0653 , H01L29/1045 , H01L29/7834 , H01L29/7841
摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

34. 发明授权

US07297600B2 Methods of forming fin field effect transistors using oxidation barrier layers 有权
标题翻译：使用氧化阻挡层形成鳍状场效应晶体管的方法
公开(公告)号：US07297600B2
公开(公告)日：2007-11-20
申请号：US11020899
申请日：2004-12-23
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7854 , B82Y10/00 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/78645
摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.
摘要翻译：在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。在鳍状有源区的上表面和相对侧壁上形成氧化物层。在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。还讨论了相关设备。

35. 发明申请

US20070128779A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070128779A1
公开(公告)日：2007-06-07
申请号：US11633403
申请日：2006-12-04
申请人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
发明人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
IPC分类号： H01L21/84 , H01L31/113
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11573
摘要： Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
摘要翻译：露出的是半导体器件及其制造方法。该装置包括设置在活性图案和基底之间的绝缘膜，其提供各种改进。这种结构提高了高集成度的效率，为半导体器件提供了先进的结构。

36. 发明授权

US07214987B2 Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same 有权
标题翻译：具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法
公开(公告)号：US07214987B2
公开(公告)日：2007-05-08
申请号：US11011911
申请日：2004-12-13
申请人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
发明人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L27/10802 , H01L27/0214 , H01L27/10873 , H01L29/7841 , H01L29/78612
摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.
摘要翻译：根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。掩埋绝缘层插入在下半导体衬底和上硅图案之间。穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时，漏极电压施加到该区域。

37. 发明申请

US20050269629A1 Fin field effect transistors and methods of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20050269629A1
公开(公告)日：2005-12-08
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/84 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

38. 发明申请

US20050227424A1 Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
标题翻译：具有场效应晶体管的半导体器件及其制造方法
公开(公告)号：US20050227424A1
公开(公告)日：2005-10-13
申请号：US11090740
申请日：2005-03-24
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Jeong-Dong Choe
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Jeong-Dong Choe
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L29/06 , H01L29/786
CPC分类号： H01L29/785 , H01L29/0653 , H01L29/66795 , H01L29/7851 , H01L29/78687 , Y10S438/933
摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.
摘要翻译：提供具有场效应晶体管的半导体器件及其形成方法。半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。栅电极优选地跨过器件有源图案，由栅极绝缘层插入。支撑图案优选地插入在器件活性图案和基底之间。支撑图案可以设置在栅电极下方。填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。填充绝缘图案可以设置在源极/漏极区域下方。栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

39. 发明授权

US06951785B2 Methods of forming field effect transistors including raised source/drain regions 有权
标题翻译：形成包括升高的源极/漏极区域的场效应晶体管的方法
公开(公告)号：US06951785B2
公开(公告)日：2005-10-04
申请号：US10832080
申请日：2004-04-26
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Chang-Sub Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Chang-Sub Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L29/66537 , H01L29/66553
摘要： A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.
摘要翻译：形成场效应晶体管的方法可以包括在半导体衬底的表面上形成掺杂层，并且在半导体衬底的表面上形成通过掺杂层的沟槽，同时保持掺杂层在槽的相对侧上的部分。可以在沟槽的表面上形成栅极绝缘层，并且可以在沟槽中的栅极绝缘层上形成栅电极。

40. 发明申请

US20050112851A1 Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures 有权
标题翻译：形成具有多沟道MOS晶体管和相关中间结构的半导体器件的方法
公开(公告)号：US20050112851A1
公开(公告)日：2005-05-26
申请号：US10974410
申请日：2004-10-27
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
IPC分类号： H01L21/00 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66484 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7831 , H01L29/78696
摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.
摘要翻译：在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。交替层叠栅极层和沟道层。在初步活性图案上形成硬掩模。使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。源极/漏极层形成在有源沟道图案和表面的暴露侧面上。选择性地蚀刻栅极层以形成隧道。门将包围活动通道模式并填充隧道。还公开了相关的中间结构。

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