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31. 发明授权

US08552468B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08552468B2
公开(公告)日：2013-10-08
申请号：US12724987
申请日：2010-03-16
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/74
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/0843 , H01L29/1095 , H01L29/4236 , H01L29/4238
摘要： A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.
摘要翻译：半导体层具有第一导电类型的第一层，第二导电类型的第二层和第三层。第三层具有第一导电类型的第一区域和第二导电类型的第二区域。第二电极与第一和第二区域中的每一个接触。在半导体层的与面对第一电极的表面相对的表面上形成沟槽。栅电极嵌入在沟槽中，其间插入有栅极绝缘膜。栅电极包括通过第一区和第二层伸入第一层的第一部分，通过第二区和第二层突出到第一层的第二部分。第二部分比第一部分伸入第一层的深度深入第一层。

32. 发明授权

US08530966B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08530966B2
公开(公告)日：2013-09-10
申请号：US13205085
申请日：2011-08-08
申请人： Atsushi Narazaki , Hisaaki Yoshida , Kazuaki Higashi
发明人： Atsushi Narazaki , Hisaaki Yoshida , Kazuaki Higashi
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238 , H01L29/7811
摘要： A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.
摘要翻译：半导体器件包括从P基层的表面延伸到P阱层的表面的沟槽。沟槽具有限定在P阱层的表面中并且在沟槽延伸的方向上的沟槽端部。沟渠有第一和第二区域。第一区域从沟槽末端部延伸到P基层与P阱层之间的边界附近的P基层的表面。第二区域从第一区域的端部在P基层的表面延伸。沟道宽度在第一区域比在第二区域中大。

33. 发明授权

US08178365B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08178365B2
公开(公告)日：2012-05-15
申请号：US13011263
申请日：2011-01-21
申请人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
发明人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
IPC分类号： G01R31/26
CPC分类号： H01L22/20 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.
摘要翻译：准备了在其表面上形成有IGBT元件和晶体管的半导体晶片。电子束在半导体晶片的整个表面上发射。在IGBT元件和晶体管中形成复合中心。通过测量装置测量晶体管的导通电压，并且通过规定的退火处理来恢复在IGBT元件和晶体管中限定的寿命。当寿命恢复时，控制装置基于所测量的晶体管的导通电压来控制退火处理中的退火处理量，使得IGBT元件的导通电压各自等于期望的导通电压。从半导体晶片获得的多个IGBT元件的导通电压的变化减小。

34. 发明授权

US08124533B2 Method of manufacturing power semiconductor device 有权
标题翻译：功率半导体器件制造方法
公开(公告)号：US08124533B2
公开(公告)日：2012-02-28
申请号：US12558999
申请日：2009-09-14
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L21/311
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66348 , H01L29/66719 , H01L29/66734 , H01L29/7397
摘要： A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film.
摘要翻译：在第一层上形成具有多个开口的掩模层。通过使用掩模层引入杂质，在第一层上形成具有不同于第一导电类型的第二导电类型的第二层。通过使用掩模层引入杂质，在第二层上形成具有第一导电类型的第三层。通过使用至少包括掩模层的蚀刻掩模进行蚀刻来形成延伸穿过第二层和第三层到第一层的沟槽。形成覆盖沟槽侧壁的栅极绝缘膜。填充沟槽的沟槽栅极形成在栅极绝缘膜上。

35. 发明申请

US20110298485A1 SEMICONDUCTOR DEVICE TEST METHOD AND APPARATUS, AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件测试方法和设备，以及半导体器件
公开(公告)号：US20110298485A1
公开(公告)日：2011-12-08
申请号：US13042600
申请日：2011-03-08
申请人： Atsushi NARAZAKI
发明人： Atsushi NARAZAKI
IPC分类号： G01R1/067 , G01R31/26 , H01L23/48
CPC分类号： G01R31/026 , G01R31/2853 , H01L2924/0002 , H01L2924/00
摘要： A method of testing a semiconductor device includes a conductive foreign matter test step of measuring the resistance value between the first and second conductive patterns to determine whether conductive foreign matter is present between the first and second conductive patterns, a first open circuit test step of measuring the resistance value between two points on the first conductive pattern to determine whether there is an open circuit in the first conductive pattern, and a second open circuit test step of measuring the resistance value between two points on the second conductive pattern to determine whether there is an open circuit in the second conductive pattern. The measurement of the resistance value in each of the test steps is accomplished by pressing probes vertically against the first conductive pattern or the second conductive pattern or both.
摘要翻译：一种测试半导体器件的方法包括：导电异物测试步骤，测量第一和第二导电图案之间的电阻值，以确定导电异物是否存在于第一和第二导电图案之间;第一开路测试步骤，测量确定第一导电图案中的两点之间的电阻值，以确定第一导电图案中是否存在开路;以及第二开路测试步骤，测量第二导电图案上的两个点之间的电阻值，以确定是否存在第二导电图案中的开路。每个测试步骤中的电阻值的测量通过将探针垂直地压靠在第一导电图案或第二导电图案上或两者来实现。

36. 发明申请

US20110244604A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110244604A1
公开(公告)日：2011-10-06
申请号：US13011263
申请日：2011-01-21
申请人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
发明人： Atsushi Narazaki , Yukio Matsushita , Masashi Osaka , Shunsuke Sakamoto
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.
摘要翻译：准备了在其表面上形成有IGBT元件和晶体管的半导体晶片。电子束在半导体晶片的整个表面上发射。在IGBT元件和晶体管中形成复合中心。通过测量装置测量晶体管的导通电压，并且通过规定的退火处理来恢复在IGBT元件和晶体管中限定的寿命。当寿命恢复时，控制装置基于所测量的晶体管的导通电压来控制退火处理中的退火处理量，使得IGBT元件的导通电压各自等于期望的导通电压。从半导体晶片获得的多个IGBT元件的导通电压的变化减小。

37. 发明申请

US20110089487A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110089487A1
公开(公告)日：2011-04-21
申请号：US12836922
申请日：2010-07-15
申请人： Kazunari NAKATA , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
发明人： Kazunari NAKATA , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a strip shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.
摘要翻译：半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。栅极结构在平面图中形成为带状。导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。

38. 发明申请

US20110084354A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110084354A1
公开(公告)日：2011-04-14
申请号：US12845176
申请日：2010-07-28
申请人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/0615 , H01L29/063 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/66128 , H01L29/7811 , H01L29/8611
摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.
摘要翻译：在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。此外，在凹部上方的绝缘膜上形成场板电极。

39. 发明申请

US20100308401A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100308401A1
公开(公告)日：2010-12-09
申请号：US12724987
申请日：2010-03-16
申请人： Atsushi NARAZAKI
发明人： Atsushi NARAZAKI
IPC分类号： H01L29/78
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/0843 , H01L29/1095 , H01L29/4236 , H01L29/4238
摘要： A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.
摘要翻译：半导体层具有第一导电类型的第一层，第二导电类型的第二层和第三层。第三层具有第一导电类型的第一区域和第二导电类型的第二区域。第二电极与第一和第二区域中的每一个接触。在半导体层的与面对第一电极的表面相对的表面上形成沟槽。栅电极嵌入在沟槽中，其间插入有栅极绝缘膜。栅电极包括通过第一区和第二层伸入第一层的第一部分，通过第二区和第二层突出到第一层的第二部分。第二部分比第一部分伸入第一层的深度深入第一层。

40. 发明申请

US20100289110A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100289110A1
公开(公告)日：2010-11-18
申请号：US12650957
申请日：2009-12-31
申请人： Yoichiro TARUI , Atsushi Narazaki , Ryoichi Fujii
发明人： Yoichiro TARUI , Atsushi Narazaki , Ryoichi Fujii
IPC分类号： H01L23/58
CPC分类号： H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1608 , H01L29/408 , H01L29/7811 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.
摘要翻译：使用一个或多个保护环的半导体器件包括围绕pn结区域的p型保护环区域，覆盖p型保护环区域的绝缘膜，与p型保护环区域电连接的一个或多个导电膜通过在绝缘膜中形成的一个或多个接触孔，以及覆盖绝缘膜和导电膜的半绝缘膜。因此，即使异物等附着在导电膜的表面，也能够确保期望的击穿电压特性。

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