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31. 发明授权

US5299092A Plastic sealed type semiconductor apparatus 失效
标题翻译：塑料密封型半导体装置
公开(公告)号：US5299092A
公开(公告)日：1994-03-29
申请号：US886859
申请日：1992-05-22
申请人： Akihiro Yaguchi , Asao Nishimura , Makoto Kitano , Ichiro Anjoh , Junichi Arita
发明人： Akihiro Yaguchi , Asao Nishimura , Makoto Kitano , Ichiro Anjoh , Junichi Arita
IPC分类号： H01L25/18 , H01L23/495 , H01L25/065 , H01L25/07 , H05K7/00 , H01L23/28
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/49551 , H01L2224/32245 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01079 , H01L2924/1815
摘要： A plastic sealed type semiconductor apparatus includes at least two semiconductor devices which are disposed with a space therebetween in such a manner that circuit forming surfaces oppose each other, and an electric signal lead which is adhered to each of the circuit forming surfaces with an insulating member provided therebetween for electric insulation and which is electrically connected to the semiconductor device by a thin metal wire. The semiconductor devices and the electric signal leads are sealed with a resin in a state where the electric signal leads are laid on top of one another to form a plastic package. The overlaid portion of the electric signal leads has a surface contact portion of the leads and a resin providing portion. The resin providing portion is a recessed portion which is formed when the resin is molded in such a manner that it passes through the surface contact portion of the leads in the lateral direction thereof. The resin providing portion prevents entry of water or moisture and thus eliminates corrosion or breakage of the electric interconnections formed on the circuit forming surface of the semiconductor device or thin metal wires. Thus, the reliability of the semiconductor apparatus is improved.
摘要翻译：一种塑料密封型半导体装置，包括至少两个半导体器件，它们以彼此相对的电路形成表面的方式设置有它们之间的空间;以及电信号引线，其中每个电路形成表面被绝缘部件设置在其间用于电绝缘，并且通过细金属线电连接到半导体器件。半导体器件和电信号引线在电信号引线彼此叠置的状态下用树脂密封以形成塑料封装。电信号引线的重叠部分具有引线的表面接触部分和树脂提供部分。树脂提供部分是当树脂以其横向穿过引线的表面接触部分的方式成型时形成的凹部。树脂提供部分防止水或湿气进入，从而消除在半导体器件或薄金属线的电路形成表面上形成的电互连的腐蚀或断裂。因此，提高了半导体装置的可靠性。

32. 发明授权

US5295045A Plastic-molded-type semiconductor device and producing method therefor 失效
标题翻译：塑料成型型半导体器件及其制造方法
公开(公告)号：US5295045A
公开(公告)日：1994-03-15
申请号：US791551
申请日：1991-11-14
申请人： Makoto Kitano , Asao Nishimura , Akihiro Yaguchi , Nae Yoneda , Maya Obata , Ryuji Kohno , Mitsuaki Haneda
发明人： Makoto Kitano , Asao Nishimura , Akihiro Yaguchi , Nae Yoneda , Maya Obata , Ryuji Kohno , Mitsuaki Haneda
IPC分类号： H01L23/28 , H01L23/495 , H01L23/50 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18 , H05K5/02
CPC分类号： H01L23/49575 , H01L23/4951 , H01L2224/05554 , H01L2224/32245 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/181 , H01L2924/1815 , H01L2924/19041
摘要： A plastic-molded-type semiconductor device having a high degree of integration encases a plurality of semiconductor chips in a package unit with each chip situated perpendicular to the substrate for mounting. On a surface of each chip containing circuits or on a reverse surface of the same, a lead frame is attached with an insulating material interposed therebetween. The chip and lead frame are connected with each other by using wire. The lead frame is arranged perpendicularly to another lead frame provided in parallel and connected therewith by welding. A printed circuit board may be used in place of said latter lead frame. By arranging the chips in projections made of resin, the thermal resistance of the semiconductor device is decreased. The present invention is particularly effective for a memory IC.
摘要翻译：具有高集成度的塑料模制型半导体器件将多个半导体芯片封装在封装单元中，每个芯片垂直于衬底设置用于安装。在每个芯片容纳电路的表面上或其背面上，引线框架之间插入绝缘材料。芯片和引线框架通过电线相互连接。引线框架垂直布置成并联设置的另一引线框架，通过焊接与引线框架相连接。可以使用印刷电路板代替所述后置引线框架。通过将芯片布置在由树脂制成的突起中，半导体器件的热阻降低。本发明对存储器IC特别有效。

33. 发明授权

US5159434A Semiconductor device having a particular chip pad structure 失效
标题翻译：具有特定芯片焊盘结构的半导体器件
公开(公告)号：US5159434A
公开(公告)日：1992-10-27
申请号：US649712
申请日：1991-02-01
申请人： Ryuji Kohno , Makoto Kitano , Asao Nishimura , Akihiro Yaguchi , Sueo Kawai
发明人： Ryuji Kohno , Makoto Kitano , Asao Nishimura , Akihiro Yaguchi , Sueo Kawai
IPC分类号： H01L21/60 , H01L23/495
CPC分类号： H01L24/49 , H01L23/49503 , H01L23/49531 , H01L2224/0401 , H01L2224/16 , H01L2224/32014 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01018 , H01L2924/01028 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/19107
摘要： An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conduting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.
摘要翻译：封装的半导体器件具有芯片，具有通孔的芯片焊盘以及与芯片的电极焊盘相对应的导电图案和引线。通过组合凹凸图案和导线之间的引线键合操作来获得任意的外部端子布置。有利地，在布置在任意位置的半导体芯片的引线和电极焊盘之间进行引线接合。提高了芯片的设计自由度和印刷电路板的自由度，从而实现了高的封装密度，并且印刷电路板的结构紧凑。

34. 发明授权

US4987474A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4987474A
公开(公告)日：1991-01-22
申请号：US536932
申请日：1990-06-12
申请人： Toshihiro Yasuhara , Masachika Masuda , Asao Nishimura , Naozumi Hatada , Sueo Kawai , Makoto Kitano , Hideo Miura , Akihiro Yaguchi , Gen Murakami
发明人： Toshihiro Yasuhara , Masachika Masuda , Asao Nishimura , Naozumi Hatada , Sueo Kawai , Makoto Kitano , Hideo Miura , Akihiro Yaguchi , Gen Murakami
IPC分类号： H01L23/495
CPC分类号： H01L24/32 , H01L23/4951 , H01L23/49541 , H01L23/49558 , H01L2224/02166 , H01L2224/05554 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/351
摘要： In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.
摘要翻译：在放置或放置在树脂成型包装体中的放大或放大的半导体芯片时，用于放置内部引线的空间被充分地固定的无引线框架中，为了增加占空比的目的，提供通孔树脂部分。此外，与颗粒的下表面相对应的每个引线在其宽度方向上分支成多个部分，以便减小应力。此外，在介于引线和芯片之间的绝缘片中，其较短侧面的尺寸被设定为小于颗粒的较短侧面的尺寸，以防止在端部的端部发生裂纹绝缘片。

35. 发明授权

US08282412B1 Flat cable and connection structure between flat cable and printed wiring board 失效
标题翻译：扁平电缆和印刷电路板之间的扁平电缆和连接结构
公开(公告)号：US08282412B1
公开(公告)日：2012-10-09
申请号：US13137330
申请日：2011-08-05
申请人： Akihiro Yaguchi , Takumi Kobayashi , Kenichi Murakami , Hiroaki Komatsu
发明人： Akihiro Yaguchi , Takumi Kobayashi , Kenichi Murakami , Hiroaki Komatsu
IPC分类号： H01R12/24
CPC分类号： H01R13/5804 , H01R12/62
摘要： A flat cable includes a plurality of conductors arranged in parallel, an insulating member covering the plurality of conductors, a first reinforcing member on a surface of an end portion of the insulating member, and a second reinforcing member on an opposite side of the first reinforcing member across the conductor and the insulating member. The first reinforcing member includes a reinforcing metal plate including an end portion bent toward the second reinforcing member, a covering member covering at least a portion of a periphery of the reinforcing metal plate, and an adhesive interposed between the reinforcing metal plate and the covering member and between the covering member and the insulating member to bond the reinforcing metal plate to the covering member and the covering member to the insulating member. The second reinforcing member has a rigidity greater than that of the covering member of the first reinforcing member.
摘要翻译：扁平电缆包括平行布置的多个导体，覆盖多个导体的绝缘构件，绝缘构件的端部的表面上的第一加强构件和位于第一增强件的相对侧上的第二加强构件穿过导体和绝缘构件的构件。第一加强构件包括加强金属板，该加强金属板包括朝向第二加强构件弯曲的端部，覆盖加强金属板的周边的至少一部分的覆盖构件以及插入在加强金属板和覆盖构件之间的粘合剂并且在覆盖构件和绝缘构件之间，将加强金属板与覆盖构件和覆盖构件接合到绝缘构件。第二加强构件的刚性大于第一加强构件的覆盖构件的刚性。

36. 发明申请

US20120184130A1 Flat cable and connection structure between flat cable and printed wiring board 失效
标题翻译：扁平电缆和印刷电路板之间的扁平电缆和连接结构
公开(公告)号：US20120184130A1
公开(公告)日：2012-07-19
申请号：US13137331
申请日：2011-08-05
申请人： Akihiro Yaguchi , Takumi Kobayashi , Kenichi Murakami , Hiroaki Komatsu
发明人： Akihiro Yaguchi , Takumi Kobayashi , Kenichi Murakami , Hiroaki Komatsu
IPC分类号： H01R9/03 , H01B7/08
CPC分类号： H01R12/53 , H01R12/79
摘要： A flat cable includes a plurality of conductors arranged in parallel and exposed at both end portions in a longitudinal direction thereof, an insulation film covering the plurality of conductors except the exposed both end portions, and a reinforcing member that covers the plurality of conductors along a width direction of the plurality of conductors, is provided on a surface of the insulation film in a part of a region including an edge of the insulation film, and includes a metal plate and an insulative covering layer for covering the metal plate.
摘要翻译：扁平电缆包括平行布置并在其长度方向上的两个端部露出的多个导体，覆盖除了露出的两个端部之外的多个导体的绝缘膜，以及沿着一个覆盖多个导体的加强构件多个导体的宽度方向设置在绝缘膜的包括绝缘膜的边缘的区域的一部分的表面上，并且包括用于覆盖金属板的金属板和绝缘覆盖层。

37. 发明授权

US07038322B2 Multi-chip module 失效
公开(公告)号：US07038322B2
公开(公告)日：2006-05-02
申请号：US10919331
申请日：2004-08-17
申请人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
发明人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
IPC分类号： H01L21/31
CPC分类号： H01L23/3157 , H01L23/3114 , H01L23/3171 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2225/1005 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

38. 发明授权

US06927489B1 Semiconductor device provided with rewiring layer 有权
标题翻译：设有重新布线层的半导体装置
公开(公告)号：US06927489B1
公开(公告)日：2005-08-09
申请号：US09787526
申请日：2000-03-14
申请人： Akihiro Yaguchi , Hideo Miura , Atsushi Kazama , Asao Nishimura
发明人： Akihiro Yaguchi , Hideo Miura , Atsushi Kazama , Asao Nishimura
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/485 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/10 , H01L23/3114 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05541 , H01L2224/05548 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/13 , H01L2224/13006 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/30105 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： In a small semiconductor device having external terminals on a semiconductor element and a semiconductor module mounted with the small semiconductor device, disconnection of the external terminals is prevented when a temperature change occurs under the conditions that the semiconductor device is mounted on a printed circuit board. To achieve this a projection is formed on a land which is an external terminal bonding area of the semiconductor device, and a protruded portion of the projection is bonded to the external terminal. An intervening portion of a protective film made of resin material is formed between the lands and semiconductor element.
摘要翻译：在半导体元件上具有外部端子的小半导体器件和安装有小型半导体器件的半导体模块中，在半导体器件安装在印刷电路板上的条件下发生温度变化时，可防止外部端子断开。为了实现这一点，在作为半导体器件的外部端子接合区域的焊盘上形成突起，突起的突出部分接合到外部端子。在平台和半导体元件之间形成由树脂材料构成的保护膜的中间部分。

39. 发明申请

US20050029674A1 Multi-chip module 失效
标题翻译：多芯片模块
公开(公告)号：US20050029674A1
公开(公告)日：2005-02-10
申请号：US10919331
申请日：2004-08-17
申请人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
发明人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
IPC分类号： H01L23/31 , H01L23/48 , H01L25/065 , H01L25/10
CPC分类号： H01L23/3157 , H01L23/3114 , H01L23/3171 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2225/1005 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
摘要翻译：多芯片模块具有至少两个半导体芯片。每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层土地和半导体芯片。半导体芯片通过外部端子放置在安装板上。第一半导体芯片的应力松弛层厚于第二半导体芯片的应力松弛层，该第二半导体芯片的距离其中心至位于其最外端部分的外部端子的距离小于第一半导体芯片的应力松弛层。

40. 发明授权

US06303982B2 Semiconductor device 失效
公开(公告)号：US06303982B2
公开(公告)日：2001-10-16
申请号：US09771617
申请日：2001-01-30
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L23495
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/0695 , H01L2224/85399
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

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