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    • 33. 发明申请
    • INVERTED COPLANAR WAVEGUIDE COUPLER WITH INTEGRAL MICROSTRIP CONNECTION PORTS
    • 具有整体微波连接端口的反相共振波导耦合器
    • WO2003009414A1
    • 2003-01-30
    • PCT/US2002/023045
    • 2002-07-18
    • CREE MICROWAVE, INC.
    • CRESCENZI, Emil, James, Jr.
    • H01P5/18
    • H01P5/186H05K1/0237
    • A coplanar coupler (14) for use with microstrip input and output ports includes a printed circuit substrate in which first and second metal input ports are formed on a top surface and cooperate with a metal layer on the bottom surface as microstrip lines, and a first and second metal output ports formed on the top surface which cooperate with the metal layer on the bottom surface as microstrip lines. The metal layer (24) on the bottom surface functions as a ground plane for the input ports and output ports, the metal layer being removed in a coupler region underlying at least portions of the metal input and output ports and extending therebetween. First and second metal lines (31, 32) are formed on the bottom surface in the coupler region and function as a coplanar coupler for the input and output ports. Electrical vias in the substrate interconnect the ports and the coplanar coupler.
    • 用于微带输入和输出端口的共面耦合器(14)包括印刷电路基板,其中第一和第二金属输入端口形成在顶表面上,并与底面上的金属层作为微带线配合,并且第一 以及形成在顶表面上的与金属层在底面上配合的第二金属输出端口,作为微带线。 底表面上的金属层(24)用作输入端口和输出端口的接地平面,金属层在金属输入和输出端口的至少一部分下方的耦合器区域中移除并在其间延伸。 第一和第二金属线(31,32)形成在耦合器区域的底表面上,并且用作用于输入和输出端口的共面耦合器。 衬底中的电气通孔互连端口和共面耦合器。
    • 35. 发明申请
    • SILICON ON INSULATOR DEVICE WITH IMPROVED HEAT REMOVAL AND METHOD OF MANUFACTURE
    • 具有改进的热去除的绝缘体装置上的硅和制造方法
    • WO2003041168A1
    • 2003-05-15
    • PCT/US2002/034860
    • 2002-10-30
    • CREE MICROWAVE, INC.
    • DARMAWAN, Johan, Agus
    • H01L27/01
    • H01L29/78603H01L23/3677H01L2924/0002H01L2924/10158H01L2924/3011H01L2924/00
    • A semiconductor device is fabricated in a silicon on insulator “SOI” substrate including a supporting silicon substrate (10), a silicon oxide layer supported by the substrate, and a silicon layer overlying the silicon oxide layer. An electrical component is fabricated in the silicon layer over a portion of the silicon oxide layer (12), and then the substrate opposite from the component is masked and etched. A metal layer (20) is then formed in the portion of the substrate which has been removed by etching with the metal layer providing heat removal from the component. In an alternative embodiment, the silicon oxide layer overlying the portion of the substrate is removed with the metal layer abutting the silicon layer. In fabricating the device, preferential etching is employed to remove the silicon in the substrate with the silicon oxide functioning as an etchant stop. A two step process can be employed including a first oxide etch to etch the bulk of the silicon and then a more selective but slower etch. Then, the exposed silicon oxide can then be removed, as in the alternative embodiment, by a preferential etchant of silicon oxide.
    • 在包括支撑硅衬底10的硅绝缘体“SOI”衬底,由衬底支撑的氧化硅层和覆盖氧化硅层的硅层上制造半导体器件。 在氧化硅层12的一部分上的硅层中制造电气部件,然后对与元件相对的基板进行掩模蚀刻。 然后在衬底的部分中形成金属层20,该部分已经通过蚀刻除去金属层,从该部件提供热量去除。 在替代实施例中,覆盖衬底部分的氧化硅层被去除,金属层邻接硅层。 在制造该器件时,采用优先蚀刻来去除衬底中的硅,氧化硅起蚀刻剂停止的作用。 可以采用两步法,包括第一氧化物蚀刻来蚀刻大部分硅,然后进行更多选择性但更慢的蚀刻。 然后,如在替代实施例中那样,可以通过优选的氧化硅蚀刻剂去除暴露的氧化硅。