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21. 发明申请

US20030178652A1 NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20030178652A1
公开(公告)日：2003-09-25
申请号：US10134223
申请日：2002-04-25
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L027/148 , H01L029/768 , H01L027/108 , H01L029/76 , H01L029/94
CPC分类号： H01L29/792 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L29/66833
摘要： A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.
摘要翻译：一种非易失性只读存储器件，其中字线在衬底上，字线包括金属层多晶硅线。捕获层还位于字线和基板之间。多晶硅保护线形成在衬底上，多晶硅保护线连接字线和衬底中的接地掺杂区，其中多晶硅保护线的电阻高于字线的电阻。

22. 发明申请

US20030168677A1 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
公开(公告)号：US20030168677A1
公开(公告)日：2003-09-11
申请号：US10095901
申请日：2002-03-11
发明人： Fu-Chieh Hsu
IPC分类号： H01L027/148
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

23. 发明申请

US20030146457A1 Gate electrode and method of fabricating the same 失效
标题翻译：栅电极及其制造方法
公开(公告)号：US20030146457A1
公开(公告)日：2003-08-07
申请号：US10356980
申请日：2003-02-03
发明人： Akira Hoshino , Kanta Saino , Shinichi Horiba , Tsutomu Hayakawa
IPC分类号： H01L027/148
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L21/32 , H01L29/6656
摘要： There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.
摘要翻译：提供一种制造栅电极的方法，包括以下步骤：（a）在半导体衬底的表面形成栅极氧化膜，（b）在栅极氧化膜上形成多层结构，多层包括形成在栅极氧化膜上的多晶硅层，形成在多晶硅层上的折射金属硅化物层和形成在折射金属硅化物层上的氮化硅层的结构，（c）在氮气气氛中对多层结构进行热退火从而在多晶硅层和折射金属硅化物层的侧壁上形成氮化硅膜，（d）氧化半导体衬底和多层结构。

24. 发明申请

US20030136984A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20030136984A1
公开(公告)日：2003-07-24
申请号：US10347838
申请日：2003-01-17
申请人： Semiconductor Technology Academic Research Center
发明人： Hiroo Masuda , Kazuyoshi Hara
IPC分类号： H01L027/148
CPC分类号： H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising a gate electrode which is formed on a semiconductor substrate through a gate insulating film and in which a plurality hexagonal rings are mutually connected so as to form a honeycomb structure, drain diffusion layers each formed in the semiconductor substrate on the inside of one hexagonal ring, source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein, and, insulating layers formed between respective source diffusion layers in the semiconductor substrate.
摘要翻译：提供了一种半导体器件，其包括通过栅极绝缘膜形成在半导体衬底上并且多个六边形环相互连接以形成蜂窝结构的栅电极，各个形成在半导体衬底中的漏极扩散层一个六边形环的内部形成在与形成有漏极扩散层的六边形环相邻的多个六边形环的内侧的半导体衬底中的源极扩散层，以及形成在各个源极扩散层之间的绝缘层半导体衬底。

25. 发明申请

US20030075741A1 Method of manufacturing an integrated circuit, integrated circuit obtained in accordance with said method, wafer provided with an integrated circuit obtained in accordance with the method, and system comprising an integrated circuit obtained by means of the method 有权
标题翻译：制造集成电路的方法，根据所述方法获得的集成电路，提供有根据该方法获得的集成电路的晶片，以及包括通过该方法获得的集成电路的系统
公开(公告)号：US20030075741A1
公开(公告)日：2003-04-24
申请号：US10253235
申请日：2002-09-24
发明人： Anton Petrus Maria Van Arendonk , Edwin Roks , Adrianus Johannes Mierop
IPC分类号： H01L027/148
CPC分类号： G01R31/318505 , G01R31/318511 , G01R31/3187
摘要： The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the manufacturing method, and a system comprising an integrated circuit (404) obtained by means of the manufacturing method.
摘要翻译：本发明涉及在芯片（402）上制造集成电路（404）的方法，其中模具（402）形成晶片（401）的可拆卸部分，该晶片包括通过切割相互分离的多个管芯车道（403）。该方法包括在至少一个切割通道（403）中施加金属化图案（407）以形成包括作为集成电路（404）的一部分的至少一个通信总线电路（405）的通信总线的步骤。所述步骤之后是其中根据使用通信总线电路（405）与集成电路（404）通信的预定测试方法测试集成电路（404）的步骤。该步骤之后是其中模具（402）与晶片（401）分离的下一步骤。通信总线电路（405）被设计成在晶片测试模式以及功能模式下进行通信。在集成电路（404）的测试期间，它以晶片测试模式进行通信。本发明还涉及通过制造方法获得的集成电路（404），包括通过制造方法获得的集成电路（404）的晶片（401）和包括获得的集成电路（404）的系统，通过制造方法。

26. 发明申请

US20030067019A1 Fast line dump structure for solid state image sensor 有权
标题翻译：用于固态图像传感器的快速线路转储结构
公开(公告)号：US20030067019A1
公开(公告)日：2003-04-10
申请号：US10293672
申请日：2002-11-13
发明人： Eric G. Stevens
IPC分类号： H01L027/148
CPC分类号： H01L29/76816 , H01L27/14806 , H01L27/14887
摘要： The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.
摘要翻译：本发明是用于电荷耦合器件的快速转储门（FDG）和快速泄放漏极（FDD）的结构。可以设想，电荷耦合器件是固态图像传感器的水平读出寄存器。该结构使用第三层多晶硅（或其他合适的栅极材料）形成快速转储栅极，除了用于在水平读出寄存器中形成栅极的另外两层栅极材料之外。这允许在快速转储门（FDG）下形成通道区而不使用高度掺杂的通道停止区，从而消除任何潜在的井或障碍物，其通常可能导致与其他结构发现的转移效率低下。

27. 发明申请

US20030057456A1 Semiconductor optical modulator and optical modulator integrated semiconductor laser 审中-公开
标题翻译：半导体光调制器和光调制器集成半导体激光器
公开(公告)号：US20030057456A1
公开(公告)日：2003-03-27
申请号：US10254527
申请日：2002-09-26
发明人： Hiroshi Wada
IPC分类号： H01L027/148
CPC分类号： B82Y20/00 , G02F1/01708 , G02F2001/0157 , H01S5/0265 , H01S5/042 , H01S5/0425 , H01S5/12
摘要： An electrode-absorption semiconductor optical modulator has a lower clad layer formed on a semiconductor substrate, an optical absorption layer for absorbing light formed on the lower clad layer, and an upper clad layer formed on the optical absorption layer. The electrode-absorption semiconductor optical modulator further includes a first electrode formed on a first main surface of the upper clad layer and a second electrode formed on a second main surface of the semiconductor substrate side. The first electrode is separated along a light proceeding direction entered from a light incident side end face of the optical modulator and the plurality of electrodes apply voltages.
摘要翻译：电极吸收半导体光调制器具有在半导体衬底上形成的下覆盖层，用于吸收形成在下包层上的光的光吸收层和形成在光吸收层上的上覆层。电极吸收半导体光调制器还包括形成在上覆盖层的第一主表面上的第一电极和形成在半导体衬底侧的第二主表面上的第二电极。第一电极沿着从光调制器的光入射侧端面进入的光行进方向分离，并且多个电极施加电压。

28. 发明申请

US20020185665A1 Photodiode and photodiode module 失效
公开(公告)号：US20020185665A1
公开(公告)日：2002-12-12
申请号：US10143956
申请日：2002-05-14
发明人： Yoshiki Kuhara , Hitoshi Terauchi
IPC分类号： H01L027/148
CPC分类号： H01L31/1035 , H01L31/0352
摘要： Besides the central pn-junction and the central electrode, a PD chip has a peripheral pn-junction and a peripheral electrode which do not appear on the sides. The ends of the peripheral pn-junction are covered with a protection layer for preventing self-shortcircuit. A reverse bias is applied to the peripheral electrode for making a wide depletion layer beneath the peripheral pn-junction. Extra carriers generated by peripherally-incidence rays are fully absorbed by the peripheral depletion layer and annihilated by the reverse bias.

29. 发明申请

US20020175350A1 Charge-coupled device 有权
标题翻译：电荷耦合器件
公开(公告)号：US20020175350A1
公开(公告)日：2002-11-28
申请号：US10055343
申请日：2002-01-22
发明人： Jan Theodoor Jozef Bosiers , Agnes Catharina Maria Kleimann , Yvonne Astrid Boersma
IPC分类号： H01L027/148 , H01L029/768 , H01L031/113
CPC分类号： H01L29/76816 , H01L27/148
摘要： The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.
摘要翻译：本发明涉及一种埋入通道型的CCD，其包括形成第一导电类型的区域（12）形式的电荷传输通道，例如n型，在相反电导率的阱（13）中类型，在示例中为p型。为了获得在一个或多个栅极（9,10a）下方的通道中的漂移场以改善电荷转移，阱具有掺杂分布，使得平均浓度在电荷传输方向上减小。这样的形状可以通过用掩模在阱注入期间覆盖阱的区域来形成，从而在栅极（9,10a）下面比在通道的其它部分下方注入更少的离子。根据本发明，可以产生组合比较大长度的门（10a），例如在输出门（9）前面的输出级中以高传输速率获得足够的存储容量。

30. 发明申请

US20020158274A1 Charge coupled device with multi-focus lengths 失效
标题翻译：电荷耦合器件具有多焦距
公开(公告)号：US20020158274A1
公开(公告)日：2002-10-31
申请号：US09840897
申请日：2001-04-25
申请人： UMAX DATA SYSTEMS INC.
发明人： Yin-Chun Huang , Chih-Wen Huang
IPC分类号： H01L027/148
CPC分类号： H01L27/14806
摘要： A charge coupled device (CCD) with multi-focus lengths is provided. The arrays of optical sensors with a plurality of transparent plates in parallel disposed thereon are disposed on a substrate. By way of either of changing the thicknesses of the transparent plates and changing the position levels of the arrays of the optical sensors, each of the arrays of the optical sensors obtains a different focal length. And thus, the depth of focus of the present charge coupled device is improved.
摘要翻译：提供了具有多焦距的电荷耦合器件（CCD）。具有平行设置在其上的多个透明板的光学传感器阵列设置在基板上。通过改变透明板的厚度和改变光学传感器的阵列的位置水平，光学传感器的每个阵列获得不同的焦距。因此，本电荷耦合器件的焦点深度得到改善。

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