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21. 发明公开

EP4383978A1 SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4383978A1
公开(公告)日：2024-06-12
申请号：EP23212528.6
申请日：2023-11-28
申请人： Samsung Electronics Co., Ltd.
发明人： AN, Hyeri , PARK, Dongsik , SHIN, Sooho , PARK, Joonsuk , PARK, Keonhee , LEE, Gaeun , CHANG, Jihoon , CHO, Yujin , CHO, Hana
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/033 , H10B12/05 , H01L28/60 , H01L28/90 , H01L28/75
摘要： A semiconductor device includes a switching element, and a data storage structure (CAP) electrically connected to the switching element. The data storage structure (CAP) includes first electrodes (170), a second electrode (168), and a dielectric layer between the first electrodes (170) and the second electrode (168). The second electrode (168) includes a compound semiconductor layer (168a) doped with an impurity element, the compound semiconductor layer (168a) includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer (168a) is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer (168a) is in a range of about 10 at % to about 15 at %.

22. 发明公开

EP4380331A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-实审
公开(公告)号：EP4380331A1
公开(公告)日：2024-06-05
申请号：EP23189041.9
申请日：2023-08-01
申请人： Samsung Electronics Co., Ltd.
发明人： JUNG, Myunghun , SHIN, Donghwa , YEO, Sung-Jin , RYU, Ho-In
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/50 , H10B12/09 , H10B12/315
摘要： A semiconductor device may include a substrate including a core region, a cell block region, and a peripheral region, which are sequentially arranged in a first direction, and a bit line structure on the cell block region. The bit line structure may include a first bit line and a second bit line, which extend in the first direction and are adjacent to each other in a second direction crossing the first direction, a bit line connector, which electrically connects the first bit line to the second bit line and is adjacent to the peripheral region, and a bit line pad, which is electrically connected to the first bit line and is adjacent to the core region.

23. 发明公开

EP4365954A1 SEMICONDUCTOR MEMORY DEVICE 审中-实审
公开(公告)号：EP4365954A1
公开(公告)日：2024-05-08
申请号：EP23183279.1
申请日：2023-07-04
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Changsik , NA, Jae Won , SONG, Junhwa , PARK, Dong-Sik
IPC分类号： H01L29/24 , H10B12/00
CPC分类号： H10B12/488 , H10B12/315 , H01L29/247
摘要： A semiconductor memory device may include a plurality of bit lines (BL) extending in a first direction on a substrate (SUB), a plurality of active pillars (ACP) respectively on the bit lines (BL), a word line (WL) extending in a second direction along the plurality of active pillars (ACP), a plurality of landing pads (LP) respectively on the plurality of active pillars (ACP), and a plurality of data storage patterns (DSP) respectively on the plurality of landing pads (LP). Each of the plurality of active pillars (ACP) may have a length extending in a direction perpendicular to an upper surface of the substrate (SUB). The word line (WL) has a wavy shape when viewed in a plan view.

24. 发明公开

EP4436329A1 INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：EP4436329A1
公开(公告)日：2024-09-25
申请号：EP24150208.7
申请日：2024-01-03
申请人： Samsung Electronics Co., Ltd.
发明人： PARK, Chanhoon , KIM, Jongkyu , KIM, Seunghoon , PARK, Sohyun , LEE, Woohyun
IPC分类号： H10B12/00
CPC分类号： H10B12/09 , H10B12/482 , H10B12/0335 , H10B12/053 , H10B12/315
摘要： An integrated circuit device includes a substrate having an active area, a plurality of bit line structures on the substrate, the plurality of bit line structures including insulating spacers on sidewalls thereof, a buried contact between the plurality of bit line structures and electrically connected to the active area, an insulation capping pattern on a bit line structure of the plurality of bit line structures, and a landing pad electrically connected to the buried contact, the landing pad arranged to vertically overlap the bit line structure on the insulation capping pattern, wherein an uppermost surface of the landing pad is higher than an uppermost surface of the insulation capping pattern, relative to the substrate.

25. 发明授权

EP4092725B1 MEMORY PRODUCTION METHOD 有权
公开(公告)号：EP4092725B1
公开(公告)日：2024-09-11
申请号：EP21881352.5
申请日：2021-07-13
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/0335 , H10B12/482 , H10B12/053 , H10B12/34

26. 发明公开

EP4415497A2 SEMICONDUCTOR MEMORY DEVICE 审中-实审
公开(公告)号：EP4415497A2
公开(公告)日：2024-08-14
申请号：EP23205348.8
申请日：2023-10-23
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Wonsok , LEE, Juho , KIM, Seunghyun , JUNG, Wooje , CHO, Minhee
IPC分类号： H10B12/00 , H01L29/786
CPC分类号： H10B12/05 , H01L29/7869 , H10B12/0335 , H10B12/315 , H01L29/78642
摘要： A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

27. 发明公开

EP4404711A1 SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4404711A1
公开(公告)日：2024-07-24
申请号：EP23218813.6
申请日：2023-12-20
申请人： Samsung Electronics Co., Ltd.
发明人： RIM, Taiuk , LEE, Jinseong , CHAE, Kyosuk
IPC分类号： H10B12/00
CPC分类号： H10B12/053 , H10B12/09 , H10B12/315 , H10B12/50
摘要： A semiconductor device may include a substrate including a cell region and a peripheral circuit region, a first gate structure in the cell region of the substrate, the first gate structure extending in a first direction parallel to an upper surface of the substrate, bit line structures on the cell region of the substrate, the bit line structures extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate, a second gate structure on the peripheral circuit region of the substrate, contact plug structures between the bit line structures, the contact plug structures contacting the substrate, first conductive structures on peripheral circuit region of the substrate, the first conductive structures being electrically connected to the peripheral circuit region of the substrate, a first upper insulation structure between the first conductive structures, the first upper insulation structure including a first upper insulation pattern and a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern, and a second upper insulation pattern between upper portions of the contact plug structures.

28. 发明公开

EP4404709A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP4404709A1
公开(公告)日：2024-07-24
申请号：EP23193863.0
申请日：2023-08-29
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Kiseok , KIM, Keunnam , KIM, Hui-Jung
IPC分类号： H10B12/00
CPC分类号： H10B12/053 , H10B12/315 , H10B12/0335 , H10B12/34
摘要： A semiconductor device including: a device isolation part on a substrate to define first to fourth active regions, the device isolation part interposed between the first and second active regions and the third and fourth active regions; first and second word lines crossing the first and second active regions and adjacent to each other; a first impurity region in the first active region between the first and second word lines; a second impurity region in the first active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad contacting the first impurity region; a second conductive pad contacting the second impurity region; a bit line on the first conductive pad; a storage node contact on the second conductive pad; and a landing pad on the storage node contact.

29. 发明公开

EP4376568A1 SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR, BIT LINE AND PERIPHERAL GATE 审中-实审
公开(公告)号：EP4376568A1
公开(公告)日：2024-05-29
申请号：EP23211234.2
申请日：2023-11-21
申请人： Samsung Electronics Co., Ltd.
发明人： SHIN, Joongchan , LEE, Kiseok , PARK, Seokhan , SHIN, Seokho
IPC分类号： H10B53/40 , H10B53/50 , H10B12/00 , H01L21/18
CPC分类号： H10B12/0335 , H10B12/033 , H10B12/09 , H10B12/482 , H10B12/50 , H10B12/315 , H01L21/185 , H10B53/50 , H10B53/40
摘要： A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.

30. 发明授权

EP4148793B1 VERTICAL-CHANNEL CELL ARRAY TRANSISTOR STRUCTURE AND DRAM DEVICE INCLUDING THE SAME 有权
公开(公告)号：EP4148793B1
公开(公告)日：2024-04-24
申请号：EP22163047.8
申请日：2022-03-18
IPC分类号： H10B12/00 , H01L21/768 , H01L23/532
CPC分类号： H10B12/315 , H10B12/488

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