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21. 发明申请

US20130027235A1 Self-Calibrated DAC with Reduced Glitch Mapping 有权
标题翻译：自校准DAC具有减少的毛刺映射
公开(公告)号：US20130027235A1
公开(公告)日：2013-01-31
申请号：US13192950
申请日：2011-07-28
申请人： James J. Riches
发明人： James J. Riches
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/0651 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog converter (DAC) is disclosed. According to some embodiments of the present disclosure, a DAC may include a plurality of current-steering elements, wherein each respective current-steering element is configured to operate as instructed by a respective calibration signal during respective steps in a calibration cycle, and at least one current-steering element is configured to operate as instructed by a first control signal during at least a first step in which the at least one current-steering element is not being calibrated, and operate as instructed by a second control signal during at least a second step in which the at least one current-steering element is not being calibrated.
摘要翻译：公开了一种数模转换器（DAC）。根据本公开的一些实施例，DAC可以包括多个电流导引元件，其中每个相应的电流导引元件被配置为在校准周期的相应步骤期间按照相应校准信号的指示进行操作，并且至少一个电流导引元件被配置为在至少一个电流导引元件未被校准的至少第一步骤期间按照第一控制信号的指示进行操作，并且在至少一个电流导引元件的至少一个所述至少一个电流导向元件未被校准的第二步骤。

22. 发明授权

US07026967B2 Method for calibrating a digital-to-analog converter and a digital-to-analog converter 有权
标题翻译：用于校准数模转换器和数模转换器的方法
公开(公告)号：US07026967B2
公开(公告)日：2006-04-11
申请号：US10970393
申请日：2004-10-22
申请人： Petri Eloranta
发明人： Petri Eloranta
IPC分类号： H03M1/10
CPC分类号： H03M1/0651 , H03M1/1033 , H03M1/682 , H03M1/687 , H03M1/747
摘要： The invention describes a method for digitally calibrating a segmented current-steering D/A-converter. One embodiment of the present invention is a 14-bit DAC, where 6 MSB's are converted with two unweighted current source array. Further, in this invention a new method for organising the switching order based on the analysed data of mismatch of the current sources is presented. A programmable mapping device is used instead of the fixed thermometer decoding before the switch array. Using this programmable mapping device the switching order of the current switches can be selected optimally so that the error in the resulting analog signal is minimised. The switching order is programmed to the mapping device on the basis of the calibration method according to the present invention. The inventive amendment is aimed at processing errors which cause poor matching inside the component itself. This amendment is done by rearranging unweighted unity current switches into a more optimum order.
摘要翻译：本发明描述了一种用于数字校准分段电流导向D / A转换器的方法。本发明的一个实施例是14位DAC，其中6个MSB被转换为两个未加权的电流源阵列。此外，在本发明中，提出了一种用于基于分析的当前源的不匹配数据来组织切换顺序的新方法。在开关阵列之前，使用可编程映射设备代替固定温度计解码。使用该可编程映射设备，可以最佳地选择电流开关的开关顺序，使得最终模拟信号中的误差最小化。基于根据本发明的校准方法将切换顺序编程到映射设备。本发明的修正旨在处理导致部件本身内部不良匹配的错误。该修正是通过将未加权的单位电流开关重新排列成更优化的顺序完成的。

23. 发明申请

US20050052297A1 Method for calibrating a digital-to-analog converter and a digital-to-analog converter 有权
标题翻译：用于校准数模转换器和数模转换器的方法
公开(公告)号：US20050052297A1
公开(公告)日：2005-03-10
申请号：US10970393
申请日：2004-10-22
申请人： Petri Eloranta
发明人： Petri Eloranta
IPC分类号： H03M1/10 , H03M1/68 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0651 , H03M1/1033 , H03M1/682 , H03M1/687 , H03M1/747
摘要： The invention describes a method for digitally calibrating a segmented current-steering D/A-converter. One embodiment of the present invention is a 14-bit DAC, where 6 MSB's are converted with two unweighted current source array. Further, in this invention a new method for organising the switching order based on the analysed data of mismatch of the current sources is presented. A programmable mapping device is used instead of the fixed thermometer decoding before the switch array. Using this programmable mapping device the switching order of the current switches can be selected optimally so that the error in the resulting analog signal is minimised. The switching order is programmed to the mapping device on the basis of the calibration method according to the present invention. The inventive amendment is aimed at processing errors which cause poor matching inside the component itself. This amendment is done by rearranging unweighted unity current switches into a more optimum order.
摘要翻译：本发明描述了一种用于数字校准分段电流导向D / A转换器的方法。本发明的一个实施例是14位DAC，其中6个MSB被转换为两个未加权的电流源阵列。此外，在本发明中，提出了一种用于基于分析的当前源的不匹配数据来组织切换顺序的新方法。在开关阵列之前，使用可编程映射设备代替固定温度计解码。使用该可编程映射设备，可以最佳地选择电流开关的开关顺序，使得最终模拟信号中的误差最小化。基于根据本发明的校准方法将切换顺序编程到映射设备。本发明的修正旨在处理导致部件本身内部不良匹配的错误。该修正是通过将未加权的单位电流开关重新排列成更优化的顺序完成的。

24. 发明申请

US20020021236A1 CMOS DAC with high impedance differential current drivers 失效
公开(公告)号：US20020021236A1
公开(公告)日：2002-02-21
申请号：US09837928
申请日：2001-04-19
申请人： Pivotal Technologies Corp.
发明人： David Vetea Greig
IPC分类号： H03M001/66
CPC分类号： H03M1/0604 , H03M1/0651 , H03M1/685
摘要： High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.

25. 发明授权

US06317066B1 Layout arrangement of current sources in a current-mode digital-to-analog converter 有权
标题翻译：电流模式数模转换器中电流源的布局布置
公开(公告)号：US06317066B1
公开(公告)日：2001-11-13
申请号：US09522290
申请日：2000-03-09
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： H03M166
CPC分类号： H03M1/0651 , H03M1/68 , H03M1/742
摘要： A current source layout arrangement for a current-mode D/A converter is disclosed. The D/A converter has a plurality of large current sources and a plurality of small current sources. Each large current source has a plurality of unit current sources, and the large current sources are divided into a plurality of groups, each consisting of two large current sources, for being symmetrically arranged. The unit current sources of two large current sources in one group are interlacingly interposed. Each small current source has at least one current source unit. The unit current sources of the small current sources are diagonally inserted into the arrangement of the unit current sources of the large current sources.
摘要翻译：公开了一种用于电流模式D / A转换器的电流源布局布置。 D / A转换器具有多个大电流源和多个小电流源。每个大电流源具有多个单位电流源，并且大电流源被分成多个组，每个组由两个大电流源组成，用于对称布置。一组中两个大电流源的单位电流源交错插入。每个小电流源具有至少一个电流源单元。小电流源的单位电流源对角线插入到大电流源的单位电流源的布置中。

26. 发明授权

US06295012B1 CMOS DAC with high impedance differential current drivers 失效
标题翻译： CMOS DAC具有高阻抗差分电流驱动器
公开(公告)号：US06295012B1
公开(公告)日：2001-09-25
申请号：US09383068
申请日：1999-08-25
申请人： David Vetea Greig
发明人： David Vetea Greig
IPC分类号： H03M166
CPC分类号： H03M1/0604 , H03M1/0651 , H03M1/685
摘要： High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.
摘要翻译：公开了适用于用低电压，低功率集成电路制造工艺实现的系统的高性能数模转换（DAC）。编码器电路接收寻求模拟表示的二进制数。二进制数字段是温度计编码和补码，以提供信号来驱动模拟转换电路。模拟转换电路包括当前单元的集合，其中一组中的每个单元对转换器的模拟输出的互补支路中的一个或另一个贡献相等的量。每个电流单元是具有电荷消除的完全差分电流开关，由调节共源共栅电流源馈电。调节型共源共栅电流源提供了非常特性的高阻抗，即使在低电压，低功耗实现中也有助于良好的电路性能。当前单元的其他设计因素对整体性能有重要贡献。还采用分层梯度对称消除技术来减少归因于过程相关表面梯度的积分非线性。

27. 发明授权

US5162800A Digital-to-analog converting unit with improved linearity 失效
标题翻译：具有改善线性的数字到模拟转换单元
公开(公告)号：US5162800A
公开(公告)日：1992-11-10
申请号：US776197
申请日：1991-10-15
申请人： Takeshi Ogawara
发明人： Takeshi Ogawara
IPC分类号： H03M1/74 , H03M1/06 , H03M1/68
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/747
摘要： A digital-to-analog converting unit decodes a digital input signal into a decoded signal, and selectively allows constant-current cells arranged in matrix to supply unit currents for producing an analog output signal, wherein a decoding circuit incorporated in the digital-to-analog converting unit sequentially selects the constant-current cells in such a manner that insufficient increment of current produced by one of the constant-current-cells cancels out excessive increment of current produced by another constant-current cell so that the analog output signal is improved in linearity.

28. 发明公开

EP2872997A4 METHODS, DEVICES, AND SYSTEMS FOR SWITCHED CAPACITOR ARRAY CONTROL TO PROVIDE MONOTONIC CAPACITOR CHANGE DURING TUNING 审中-公开
标题翻译：方法，装置和系统控制开关电容器装置，用于单调的电容变化在表决时
公开(公告)号：EP2872997A4
公开(公告)日：2016-06-29
申请号：EP13816182
申请日：2013-06-12
申请人： WISPRY INC
发明人： MORRIS ARTHUR S III
IPC分类号： G06F12/00 , G06F7/64 , G06F7/66 , H03M1/06 , H03M1/08 , H03M1/66
CPC分类号： H03H19/004 , H03J2200/10 , H03M1/0651 , H03M1/0665 , H03M1/0863 , H03M1/66

29. 发明授权

EP0903861B1 Method for selecting a sequence of cells inside a bidimensional matrix structure of a digital-analog converter and corresponding converter 失效
标题翻译：一种用于在数字 - 模拟转换器的一个二维矩阵结构选择小区流，并根据工作转换器的此方法的方法
公开(公告)号：EP0903861B1
公开(公告)日：2003-04-23
申请号：EP97402193.3
申请日：1997-09-19
申请人： ALCATEL
发明人： Louagie, Filip Marcel , Chang, Zhong Yuan , Cornil, Jean-Philippe
IPC分类号： H03M1/06
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/747

30. 发明授权

EP0399456B1 D/A converter having improved segment arrangement 失效
标题翻译： D /与区段布置A转换器
公开(公告)号：EP0399456B1
公开(公告)日：1996-07-24
申请号：EP90109684.2
申请日：1990-05-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsuji, Kazuhiro, c/o Intellectual Property Div. , Iida, Tetsuya, c/o Intellectual Property Div. , Satoh, Takayuki, c/o Intellectual Property Div.
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/0651 , H03M1/685 , H03M1/765

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