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    • 24. 发明公开
    • 비동기 그레이-코드 카운터
    • 不同寻常的灰色代码计数器
    • KR1020070002892A
    • 2007-01-05
    • KR1020050058590
    • 2005-06-30
    • 엘지디스플레이 주식회사
    • 이부열
    • H03M7/16
    • H03K23/005H03K23/001
    • An asynchronous gray-code counter is provided to increase the circuit size, as removing a glitch phenomenon in the asynchronous counter by adding a minimum number of flip flops. An Nth flip flop(DF11) outputs a first output signal according to a clock signal. A (N+1)th flip flop(DF12) receives the first output signal of the Nth flip flop as an input signal, and then outputs an output signal according to the clock signal, and supplies an input signal of the Nth flip flop at the same time. A (N+2)th flip flop(DF13) receives the output signal of the (N+1)th flip flop as a clock signal and outputs a second output signal having a half period of the first output signal, and feeds back an input signal at the same time. A (N+3)th flip flop(DF14) receives an inverted output signal of the (N+1)th flip flop as a clock signal, and outputs a third output signal having a half period of the second output signal. A (N+4)th flip flop(DF15) receives the third output signal of the (N+3)th flip flop as an input signal, and outputs a fourth output signal having a half period of the third output signal according to the same clock signal as the (N+3)th flip flop.
    • 提供了一个异步灰度计数器来增加电路尺寸,通过添加最少数量的触发器来消除异步计数器中的毛刺现象。 第N触发器(DF11)根据时钟信号输出第一输出信号。 A(N + 1)触发器(DF12)接收第N个触发器的第一输出信号作为输入信号,然后根据时钟信号输出输出信号,并将第N个触发器的输入信号 同一时间。 A(N + 2)触发器(DF13)接收第(N + 1)个触发器的输出信号作为时钟信号,并输出具有第一输出信号的半周期的第二输出信号, 输入信号同时进行。 A(N + 3)触发器(DF14)接收第(N + 1)个触发器的反相输出信号作为时钟信号,并输出具有第二输出信号的半周期的第三输出信号。 A(N + 4)触发器(DF15)接收第(N + 3)个触发器的第三输出信号作为输入信号,并输出具有第三输出信号的半周期的第四输出信号 与第(N + 3)个触发器相同的时钟信号。