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21. 发明授权

US09275967B2 Protrusion bump pads for bond-on-trace processing 有权
标题翻译：用于跟踪跟踪处理的突起凸块
公开(公告)号：US09275967B2
公开(公告)日：2016-03-01
申请号：US14148482
申请日：2014-01-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Min Liang , Jiun-Yi Wu
IPC分类号： H01L23/00 , H01L23/48 , H01L21/66
CPC分类号： H01L23/49838 , H01L22/14 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/11614 , H01L2224/11622 , H01L2224/131 , H01L2224/13144 , H01L2224/13294 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/1712 , H01L2224/17132 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81815 , H01L2924/01057 , H01L2924/01072 , H01L2924/05042 , H01L2924/0533 , H01L2924/0534 , H01L2924/05342 , H01L2924/05432 , H01L2924/05442 , H01L2924/05994 , H01L2924/14 , H01L2924/1531 , H01L2924/15787 , H01L2924/2064 , H01L2924/20641 , H05K1/0268 , H05K1/113 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2201/0989 , H05K2201/10674 , H05K2203/0353 , H01L2924/014 , H01L2924/00014
摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.
摘要翻译：提供了一个管芯和一个衬底。芯片包括至少一个集成电路芯片，并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘，并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。裸片经由多个导电凸块耦合到基板，每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。

22. 发明专利

JPWO2006098196A1 半導体チップを備えた実装体およびその製造方法有权
公开(公告)号：JPWO2006098196A1
公开(公告)日：2008-08-21
申请号：JP2007508084
申请日：2006-03-08
申请人：松下電器産業株式会社
发明人：白石　司 , 司白石 , 幸宏石丸 , 幸宏石丸 , 靖治辛島 , 靖治辛島 , 中谷　誠一 , 誠一中谷 , 矢部　裕城 , 裕城矢部
IPC分类号： H01L21/60
CPC分类号： H05K3/3436 , H01L21/563 , H01L23/49838 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/1703 , H01L2224/17051 , H01L2224/17132 , H01L2224/17136 , H01L2224/17151 , H01L2224/17155 , H01L2224/17177 , H01L2224/17515 , H01L2224/29111 , H01L2224/2919 , H01L2224/32052 , H01L2224/32225 , H01L2224/73204 , H01L2224/83007 , H01L2224/83097 , H01L2224/83192 , H01L2224/83801 , H01L2224/83887 , H01L2224/83888 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15747 , H01L2924/30105 , H01L2924/3025 , H05K3/323 , H05K3/3484 , H05K2201/09781 , H05K2201/10977 , H05K2203/046 , Y02P70/613 , H01L2224/1713 , H01L2224/1715 , H01L2924/00 , H01L2924/01083 , H01L2924/00014 , H01L2924/013
摘要：本発明は、生産性、信頼性が高い半導体チップを備えた実装体およびその製造方法を提供するものである。半導体チップ(10)と実装基板(30)とを備えた実装体(100)であって、半導体チップ(10)には、実装基板側に面するチップ表面(10a)に複数の素子電極(12)が形成されており、実装基板(30)には、複数の素子電極(12)のそれぞれに対応して、電極端子(32)が形成されており、実装基板(30)の電極端子(32)と、素子電極(12)とは、自己集合的に形成された半田バンプ(17)によって一括して電気的に接続されており、チップ表面(10a)、または、実装基板(30)のうちチップ表面(10a)に対応する表面(35)には、素子電極(12)および電極端子(32)に接続されていない電極パターン(20)が形成されており、そして、電極パターン(20)には半田(19)が集積されていることを特徴とする。

23. 发明申请

US20190122976A1 Protrusion Bump Pads for Bond-on-Trace Processing 审中-公开
公开(公告)号：US20190122976A1
公开(公告)日：2019-04-25
申请号：US16228928
申请日：2018-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Min Liang , Jiun Yi Wu
IPC分类号： H01L23/498 , H01L23/48 , H01L23/00 , H05K1/02 , H05K1/11 , H05K3/40 , H01L21/66
CPC分类号： H01L23/49838 , H01L22/14 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/11614 , H01L2224/11622 , H01L2224/131 , H01L2224/13144 , H01L2224/13294 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/1712 , H01L2224/17132 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81815 , H01L2924/01057 , H01L2924/01072 , H01L2924/05042 , H01L2924/0533 , H01L2924/0534 , H01L2924/05342 , H01L2924/05432 , H01L2924/05442 , H01L2924/05994 , H01L2924/14 , H01L2924/1531 , H01L2924/15787 , H01L2924/2064 , H01L2924/20641 , H05K1/0268 , H05K1/113 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2201/0989 , H05K2201/10674 , H05K2203/0353 , H01L2924/014 , H01L2924/00014
摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

24. 发明申请

US20180096959A1 SEMI-CONDUCTOR PACKAGE STRUCTURE 审中-公开
公开(公告)号：US20180096959A1
公开(公告)日：2018-04-05
申请号：US15599160
申请日：2017-05-18
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

25. 发明授权

US09859187B2 Ball grid array package with protective circuitry layout and a substrate utilized in the package 有权
公开(公告)号：US09859187B2
公开(公告)日：2018-01-02
申请号：US15385320
申请日：2016-12-20
申请人： POWERTECH TECHNOLOGY INC.
发明人： Yong-Cheng Chuang
IPC分类号： H01L23/00 , H01L23/367 , H01L23/31 , H01L23/498
CPC分类号： H01L23/3675 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/09 , H01L24/17 , H01L2224/0401 , H01L2224/17132 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2924/3512
摘要： Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.

26. 发明授权

US09679862B2 Semiconductor device having conductive bumps of varying heights 有权
公开(公告)号：US09679862B2
公开(公告)日：2017-06-13
申请号：US14555959
申请日：2014-11-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yen-Liang Lin , Tin-Hao Kuo , Sheng-Yu Wu , Chen-Shien Chen
IPC分类号： H01L23/49 , H01L23/00 , H01L21/48 , H01L23/498
CPC分类号： H01L24/17 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L2224/0345 , H01L2224/03622 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05583 , H01L2224/05655 , H01L2224/0603 , H01L2224/11462 , H01L2224/13005 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13123 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14132 , H01L2224/14135 , H01L2224/14136 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/17132 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2924/15311 , H01L2924/15724 , H01L2924/15747 , H01L2924/3511 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip includes a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

27. 发明授权

US09659895B2 Semi-conductor package structure 有权
公开(公告)号：US09659895B2
公开(公告)日：2017-05-23
申请号：US15195324
申请日：2016-06-28
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/48 , H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

28. 发明申请

US20160190084A1 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT PACKAGE AND APPARATUS PRODUCED THEREBY 有权
标题翻译：用于生产集成电路封装的方法和生产的装置
公开(公告)号：US20160190084A1
公开(公告)日：2016-06-30
申请号：US14926709
申请日：2015-10-29
申请人： PMC-SIERRA US, INC.
发明人： John PLASTERER
IPC分类号： H01L23/00 , H01L23/498 , H01L21/66 , G06F17/50
CPC分类号： H01L24/17 , H01L22/32 , H01L23/49827 , H01L23/49838 , H01L2224/13025 , H01L2224/16055 , H01L2224/16057 , H01L2224/17132
摘要： A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.
摘要翻译：提供了一种处理器实现的方法和集成电路封装。根据实施方式，制造芯片封装的方法包括在精细间距封装中的选定位置放置焊球，并在去填充的焊球位置提供测试焊盘。在示例实现中，该方法包括接收和修改包装设计。在一个实现中，集成电路封装中的一排测试焊盘设置在多个同心的环形行中，该行的测试焊盘与外部的通孔连接的焊球相邻，并且与内部一列通孔连接的焊料相邻球。在一个实现中，测试焊盘位于与PCB的面向封装表面上的至少一个通孔位置相对的位置的子集的位于面向PCB的面向表面上。测试焊盘保持大量的信号引脚，并且不会干扰通孔。

29. 发明申请

US20180323164A1 SEMI-CONDUCTOR PACKAGE STRUCTURE 审中-公开
公开(公告)号：US20180323164A1
公开(公告)日：2018-11-08
申请号：US16034917
申请日：2018-07-13
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside, to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

30. 发明申请

US20180061810A1 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20180061810A1
公开(公告)日：2018-03-01
申请号：US15372638
申请日：2016-12-08
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Chang-Fu Lin , Chin-Tsai Yao , Kuo-Hua Yu , Fu-Tang Huang
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L25/00 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L23/49811 , H01L23/5385 , H01L23/5389 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/13541 , H01L2224/16013 , H01L2224/16237 , H01L2224/1703 , H01L2224/17055 , H01L2224/17132 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/92225 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/3512 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

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