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21. 发明授权

US07649267B2 Package equipped with semiconductor chip and method for producing same 有权
标题翻译：配有半导体芯片的封装及其制造方法
公开(公告)号：US07649267B2
公开(公告)日：2010-01-19
申请号：US11884613
申请日：2006-03-08
申请人： Tsukasa Shiraishi , Yukihiro Ishimaru , Seiji Karashima , Seiichi Natkatani , Hiroki Yabe
发明人： Tsukasa Shiraishi , Yukihiro Ishimaru , Seiji Karashima , Seiichi Natkatani , Hiroki Yabe
IPC分类号： H01L29/41 , H01L21/00
CPC分类号： H05K3/3436 , H01L21/563 , H01L23/49838 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/83 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/1703 , H01L2224/17051 , H01L2224/17132 , H01L2224/17136 , H01L2224/17151 , H01L2224/17155 , H01L2224/17177 , H01L2224/17515 , H01L2224/29111 , H01L2224/2919 , H01L2224/32052 , H01L2224/32225 , H01L2224/73204 , H01L2224/83007 , H01L2224/83097 , H01L2224/83192 , H01L2224/83801 , H01L2224/83887 , H01L2224/83888 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15747 , H01L2924/30105 , H01L2924/3025 , H05K3/323 , H05K3/3484 , H05K2201/09781 , H05K2201/10977 , H05K2203/046 , Y02P70/613 , H01L2224/1713 , H01L2224/1715 , H01L2924/00 , H01L2924/01083 , H01L2924/013 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of electrode terminals (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, connection terminals (32) respectively corresponding to the plurality of electrode terminals (12), are formed on the mounting substrate (30), the connection terminals (32) on the mounting substrate (30) and the electrode terminals (12) are electrically connected collectively by solder bumps (17) formed in self-assembly, an electrode pattern (20) not connected with the electrode terminals (12) and the connection terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).
摘要翻译：具有半导体芯片的高可靠性，高生产率的封装及其制造方法。在包括半导体芯片（10）和安装基板（30）的封装（100）中，在与安装基板侧相对的半导体芯片（10）的表面（10a）上形成有多个电极端子（12）分别对应于多个电极端子（12）的连接端子（32）形成在安装基板（30）上，安装基板（30）上的连接端子（32）和电极端子（12）电连接集体地通过自组装形成的焊料凸点（17），在芯片表面（10a）或表面（35）上形成未与电极端子（12）和连接端子（32）连接的电极图案（20）对应于芯片表面（10a）的安装基板（30），并且焊料（19）积聚在电极图案（20）上。

22. 发明公开

US20240021557A1 SEMICONDUCTOR DEVICE AND BUMP ARRANGEMENT METHOD 审中-公开
公开(公告)号：US20240021557A1
公开(公告)日：2024-01-18
申请号：US17864038
申请日：2022-07-13
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kazuo SAKAMOTO
IPC分类号： H01L23/00 , H01L21/56
CPC分类号： H01L24/17 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/81 , H01L21/563 , H01L2924/35121 , H01L2924/381 , H01L2224/81911 , H01L2224/83911 , H01L2224/17132 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/17133
摘要： This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.

23. 发明申请

US20190122976A1 Protrusion Bump Pads for Bond-on-Trace Processing 审中-公开
公开(公告)号：US20190122976A1
公开(公告)日：2019-04-25
申请号：US16228928
申请日：2018-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Min Liang , Jiun Yi Wu
IPC分类号： H01L23/498 , H01L23/48 , H01L23/00 , H05K1/02 , H05K1/11 , H05K3/40 , H01L21/66
CPC分类号： H01L23/49838 , H01L22/14 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/11614 , H01L2224/11622 , H01L2224/131 , H01L2224/13144 , H01L2224/13294 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/1712 , H01L2224/17132 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81815 , H01L2924/01057 , H01L2924/01072 , H01L2924/05042 , H01L2924/0533 , H01L2924/0534 , H01L2924/05342 , H01L2924/05432 , H01L2924/05442 , H01L2924/05994 , H01L2924/14 , H01L2924/1531 , H01L2924/15787 , H01L2924/2064 , H01L2924/20641 , H05K1/0268 , H05K1/113 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2201/0989 , H05K2201/10674 , H05K2203/0353 , H01L2924/014 , H01L2924/00014
摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

24. 发明申请

US20180096959A1 SEMI-CONDUCTOR PACKAGE STRUCTURE 审中-公开
公开(公告)号：US20180096959A1
公开(公告)日：2018-04-05
申请号：US15599160
申请日：2017-05-18
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

25. 发明授权

US09859187B2 Ball grid array package with protective circuitry layout and a substrate utilized in the package 有权
公开(公告)号：US09859187B2
公开(公告)日：2018-01-02
申请号：US15385320
申请日：2016-12-20
申请人： POWERTECH TECHNOLOGY INC.
发明人： Yong-Cheng Chuang
IPC分类号： H01L23/00 , H01L23/367 , H01L23/31 , H01L23/498
CPC分类号： H01L23/3675 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/09 , H01L24/17 , H01L2224/0401 , H01L2224/17132 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2924/3512
摘要： Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.

26. 发明授权

US09679862B2 Semiconductor device having conductive bumps of varying heights 有权
公开(公告)号：US09679862B2
公开(公告)日：2017-06-13
申请号：US14555959
申请日：2014-11-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yen-Liang Lin , Tin-Hao Kuo , Sheng-Yu Wu , Chen-Shien Chen
IPC分类号： H01L23/49 , H01L23/00 , H01L21/48 , H01L23/498
CPC分类号： H01L24/17 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L2224/0345 , H01L2224/03622 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05583 , H01L2224/05655 , H01L2224/0603 , H01L2224/11462 , H01L2224/13005 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13123 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14132 , H01L2224/14135 , H01L2224/14136 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/17132 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2924/15311 , H01L2924/15724 , H01L2924/15747 , H01L2924/3511 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip includes a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

27. 发明授权

US09659895B2 Semi-conductor package structure 有权
公开(公告)号：US09659895B2
公开(公告)日：2017-05-23
申请号：US15195324
申请日：2016-06-28
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/48 , H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

28. 发明申请

US20160190084A1 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT PACKAGE AND APPARATUS PRODUCED THEREBY 有权
标题翻译：用于生产集成电路封装的方法和生产的装置
公开(公告)号：US20160190084A1
公开(公告)日：2016-06-30
申请号：US14926709
申请日：2015-10-29
申请人： PMC-SIERRA US, INC.
发明人： John PLASTERER
IPC分类号： H01L23/00 , H01L23/498 , H01L21/66 , G06F17/50
CPC分类号： H01L24/17 , H01L22/32 , H01L23/49827 , H01L23/49838 , H01L2224/13025 , H01L2224/16055 , H01L2224/16057 , H01L2224/17132
摘要： A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.
摘要翻译：提供了一种处理器实现的方法和集成电路封装。根据实施方式，制造芯片封装的方法包括在精细间距封装中的选定位置放置焊球，并在去填充的焊球位置提供测试焊盘。在示例实现中，该方法包括接收和修改包装设计。在一个实现中，集成电路封装中的一排测试焊盘设置在多个同心的环形行中，该行的测试焊盘与外部的通孔连接的焊球相邻，并且与内部一列通孔连接的焊料相邻球。在一个实现中，测试焊盘位于与PCB的面向封装表面上的至少一个通孔位置相对的位置的子集的位于面向PCB的面向表面上。测试焊盘保持大量的信号引脚，并且不会干扰通孔。

29. 发明授权

US11901389B2 Infrared sensor and imaging apparatus 有权
公开(公告)号：US11901389B2
公开(公告)日：2024-02-13
申请号：US17325308
申请日：2021-05-20
申请人： NEC Corporation
发明人： Tomo Tanaka , Kimiyoshi Fukatsu
IPC分类号： H01L27/146 , H01L23/00 , H04N5/33 , H01L25/18 , H04N25/79
CPC分类号： H01L27/14636 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L25/18 , H01L27/14649 , H04N5/33 , H04N25/79 , H01L2224/05554 , H01L2224/06131 , H01L2224/16227 , H01L2224/17132 , H01L2924/12043
摘要： An infrared sensor including: a detection substrate that includes a first substrate in which infrared detection elements are arranged in a lattice shape and first terminals each of which is associated with one of the infrared detection elements are arranged; a readout substrate that includes a second substrate in which second terminals each of which is associated with one of the first terminals are arranged and a readout circuit that reads an electrical signal based on infrared light detected by each one of the infrared detection elements is formed; and bumps that electrically connect each one of the first terminals to one of the second terminals associated with the one of the first terminals, in which at least one of the first terminals, the second terminals, or the bumps is partially arranged at a position between the infrared detection elements that are adjacent in a top view.

30. 发明申请

US20180323164A1 SEMI-CONDUCTOR PACKAGE STRUCTURE 审中-公开
公开(公告)号：US20180323164A1
公开(公告)日：2018-11-08
申请号：US16034917
申请日：2018-07-13
申请人： Intel Corporation
发明人： Xinhua Wang
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/17 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/02331 , H01L2224/16225 , H01L2224/17132
摘要： Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside, to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

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