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21. 发明申请

US20050211461A1 Flat cable conductor, method of making the same and flat cable using the same 有权
标题翻译：扁平电缆导体，制造相同的方法和使用其的扁平电缆
公开(公告)号：US20050211461A1
公开(公告)日：2005-09-29
申请号：US11044622
申请日：2005-01-28
申请人： Toshiyuki Horikoshi , Takaaki Ichikawa , Katsuo Endo , Masato Ito , Hideo Matsuo
发明人： Toshiyuki Horikoshi , Takaaki Ichikawa , Katsuo Endo , Masato Ito , Hideo Matsuo
IPC分类号： C23C30/00 , C23C2/08 , C25D5/10 , C25D5/48 , C25D7/06 , H01B1/02 , H01B5/02 , H01B7/08 , H01B13/00 , H05K1/00 , H05K3/20 , H05K3/24 , H05K3/28 , H05K3/38
CPC分类号： H05K3/244 , C25D5/10 , C25D5/50 , C25D7/0607 , H05K1/0393 , H05K3/202 , H05K3/281 , H05K3/386
摘要： A flat cable conductor has: a conductor made of copper or a copper alloy; a first plating film made of tin and/or a tin-copper alloy, the first plating film being formed around the conductor; and a second plating film made of an alloy of tin and a third element selected from Au, Ag, Ni, Ge, Zn and Bi, the second plating film being formed around the first plating film. The third element has a concentration of 0.01 or more and 80 or less wt % at an outer surface of the second plating film.
摘要翻译：扁平电缆导体具有：由铜或铜合金制成的导体; 由锡和/或锡 - 铜合金制成的第一镀膜，所述第一镀膜围绕所述导体形成; 以及由锡和选自Au，Ag，Ni，Ge，Zn和Bi的第三元素的合金制成的第二镀膜，所述第二镀膜围绕所述第一镀膜形成。第三元素在第二镀膜的外表面具有0.01重量％以上且80重量％以下的浓度。

22. 发明授权

US06862672B1 Semiconductor memory device and method of controlling same 失效
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US06862672B1
公开(公告)日：2005-03-01
申请号：US09583233
申请日：2000-05-31
申请人： Tomomi Furudate , Takaaki Ichikawa , Junya Kawamata , Hideyuki Furukawa , Haruo Shoji , Yuzuru Matsuno , Tatsuya Yoshimoto , Masato Kitamura
发明人： Tomomi Furudate , Takaaki Ichikawa , Junya Kawamata , Hideyuki Furukawa , Haruo Shoji , Yuzuru Matsuno , Tatsuya Yoshimoto , Masato Kitamura
IPC分类号： G11C11/41 , G06F12/00 , G11C8/20 , G11C16/06 , G11C16/22
CPC分类号： G11C8/20 , G11C16/22
摘要： A plurality of memory cells corresponding to an address space larger than 2n and smaller than 2(n+1), an invalid address detecting circuit, and an invalid signal outputting circuit are comprised. Upon command input, the invalid address detecting circuit invalidates a command in the case where the invalid address detecting circuit detects a fact that an address signal supplied from exterior indicates an invalid address space. Therefore, at the time of invalid address supply, internal circuits are not activated and an erroneous write or erase operation can be prevented. Since the internal circuits do not operate, power consumption can be reduced substantially. The invalid signal outputting circuit outputs an invalid signal by receiving the fact of invalid address signal detection by the invalid address detecting circuit. Therefore, a system unit mounting the semiconductor memory device can easily recognize that the invalid address signal has been supplied to the semiconductor memory device. As a result, a malfunctioning can be prevented and reliability of the system unit improves.
摘要翻译：包括对应于大于2 且小于2 <（n + 1）>的地址空间的多个存储单元，无效地址检测电路和无效信号输出电路。在命令输入时，无效地址检测电路在无效地址检测电路检测到从外部提供的地址信号表示无效地址空间的事实的情况下使命令无效。因此，在无效地址提供时，内部电路不被激活，并且可以防止错误的写入或擦除操作。由于内部电路不工作，所以能够大幅度降低功耗。无效信号输出电路通过接收无效地址检测电路的无效地址信号检测的事实来输出无效信号。因此，安装半导体存储器件的系统单元可以容易地识别出无效地址信号已被提供给半导体存储器件。结果，可以防止故障，并且系统单元的可靠性提高。

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