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21. 发明申请

US20100146350A1 TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS 有权
标题翻译：用于减少功率耗散和供电电流的测试生成方法
公开(公告)号：US20100146350A1
公开(公告)日：2010-06-10
申请号：US12703057
申请日：2010-02-09
申请人： Xijiang Lin , Janusz Rajski
发明人： Xijiang Lin , Janusz Rajski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31721 , G01R31/318357 , G01R31/318575
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
摘要翻译：这里公开的是用于生成测试图案的方法，装置和系统的代表性实施例，可用作测试图案生成过程的一部分（例如，用于自动测试图案生成器（ATPG）软件工具））。在一个示例性实施例中，为电路设计的状态元素（例如，扫描单元）确定保持概率。产生针对电路设计中的一个或多个故障的测试立方体。在一个特定实现中，测试多维数据集最初包括指定的一个或多个故障的值，并且还包括未指定的值。通过至少部分由保存概率确定的值来指定至少一部分未指定值来修改测试立方体，并存储。

22. 发明申请

US20100138708A1 DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS 有权
标题翻译：用于测试模式的低功率分解的分解器
公开(公告)号：US20100138708A1
公开(公告)日：2010-06-03
申请号：US12641150
申请日：2009-12-17
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

23. 发明授权

US07653851B2 Phase shifter with reduced linear dependency 有权
标题翻译：移相器具有减少的线性依赖性
公开(公告)号：US07653851B2
公开(公告)日：2010-01-26
申请号：US12412267
申请日：2009-03-26
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

24. 发明申请

US20090228749A1 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES 有权
标题翻译：选择性测试反应的方法和装置
公开(公告)号：US20090228749A1
公开(公告)日：2009-09-10
申请号：US12396377
申请日：2009-03-02
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

25. 发明申请

US20090183128A1 GENERATING TEST PATTERNS HAVING ENHANCED COVERAGE OF UNTARGETED DEFECTS 有权
标题翻译：生成有突出缺陷的增强测试模式
公开(公告)号：US20090183128A1
公开(公告)日：2009-07-16
申请号：US12404583
申请日：2009-03-16
申请人： Janusz Rajski , Huaxing Tang , Chen Wang
发明人： Janusz Rajski , Huaxing Tang , Chen Wang
IPC分类号： G06F17/50
CPC分类号： G01R31/31835 , G06F11/263
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于生成具有检测无目标缺陷的能力增加的测试图案的方法，装置和系统的代表性实施例。在一个示例性实施例中，例如，确定用于测试集成电路设计中的目标故障（例如，卡住故障或桥接故障）的一个或多个确定性测试值。确定在测试期间增加一个或多个非靶向缺陷的可检测性的附加测试值。创建一个或多个测试模式，其包括确定性测试值的至少一部分和附加测试值的至少一部分。还公开了包括用于使计算机执行任何公开的方法或包括由所公开的任何实施例产生的测试模式的计算机可执行指令的计算机可读介质。

26. 发明授权

US07509546B2 Test pattern compression for an integrated circuit test environment 有权
公开(公告)号：US07509546B2
公开(公告)日：2009-03-24
申请号：US11523111
申请日：2006-09-18
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

27. 发明授权

US07478296B2 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07478296B2
公开(公告)日：2009-01-13
申请号：US10354633
申请日：2003-01-29
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

28. 发明申请

US20080320352A1 METHODS FOR DISTRIBUTION OF TEST GENERATION PROGRAMS 审中-公开
标题翻译：分布测试生成程序的方法
公开(公告)号：US20080320352A1
公开(公告)日：2008-12-25
申请号：US12197892
申请日：2008-08-25
申请人： Jon Udell , Chen Wang , Mark Kassab , Janusz Rajski
发明人： Jon Udell , Chen Wang , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/3181
CPC分类号： G01R31/318314 , G01R31/31707
摘要： As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.
摘要翻译：如本文所述，电路测试算法或其部分可以以分布式方式执行，使得它们的执行可以通过处理器的网络。在一个方面，通过这种分布式执行获得的结果被确保与通过以非分布式执行它们将获得的结果一致。因此，在一个方面，算法或其部分必须被分配。算法或其部分通过将其随机数生成与彼此独立地分离来实现。该隔离也适用于与相同算法的不同调用实例相关联的任何随机数生成。在一个方面，通过确保用于算法或其部分的随机数序列的计算不依赖于为其他人计算的随机数序列或相同算法的呼叫实例之间的计算来实现隔离。

29. 发明授权

US07370254B2 Compressing test responses using a compactor 有权
标题翻译：使用压实机压缩测试响应
公开(公告)号：US07370254B2
公开(公告)日：2008-05-06
申请号：US10778950
申请日：2004-02-13
申请人： Janusz Rajski , Jerzy Tyszer , Chen Wang , Grzegorz Mrugalski , Artur Pogiel
发明人： Janusz Rajski , Jerzy Tyszer , Chen Wang , Grzegorz Mrugalski , Artur Pogiel
IPC分类号： G01R31/28
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路中的测试结果的压实机的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以例如用作任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

30. 发明授权

US07260591B2 Method for synthesizing linear finite state machines 有权
标题翻译：线性有限状态机的合成方法
公开(公告)号：US07260591B2
公开(公告)日：2007-08-21
申请号：US10781031
申请日：2004-02-17
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
摘要翻译：用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。然后确定原始电路内的反馈连接。随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

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