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21. 发明授权

US08581225B2 Variable resistance nonvolatile memory device and method of manufacturing the same 有权
标题翻译：可变电阻非易失性存储器件及其制造方法
公开(公告)号：US08581225B2
公开(公告)日：2013-11-12
申请号：US13379460
申请日：2011-04-26
申请人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
IPC分类号： H01L27/26 , H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1633
摘要： A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.
摘要翻译：一种制造方法，包括在基板上形成各自成形为条状的下层铜线，在各下层铜线上形成各自成形为条状的电极种子层，使用化学镀，在上述铜层上形成层间绝缘层电极种子层，在所述层间绝缘层中形成穿过所述层间绝缘层并延伸到所述电极种子层的存储单元孔，在使用所述无电解槽的各个存储单元孔中露出的所述电极种子层上形成贵金属电极层在各个存储单元孔中电镀，形成连接到贵金属电极层的可变电阻层，并且在层间绝缘层和可变电阻层之上形成上层铜线，每条铜线被成形为带状，连接到相应的一个可变电阻层，并穿过下层铜线。

22. 发明申请

US20130112935A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND MANUFACTURING METHOD FOR THE SAME 有权
标题翻译：非易失性存储元件，非易失性存储器件及其制造方法
公开(公告)号：US20130112935A1
公开(公告)日：2013-05-09
申请号：US13810245
申请日：2011-11-30
申请人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/1052 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.
摘要翻译：根据本发明的非易失性存储元件包括第一金属线; 形成在所述第一金属线上并连接到所述第一金属线的插头; 包括第一电极，第二电极和可变电阻层的堆叠结构，所述堆叠结构形成在连接到所述第一电极的插头上; 形成在所述堆叠结构上并直接连接到所述第二电极的第二金属线; 以及侧壁保护层，其覆盖层叠结构的侧壁，并且具有绝缘性和氧阻隔性，其中第二金属线的下表面的一部分位于堆叠结构的上表面的下方。

23. 发明授权

US08537605B2 Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof 有权
标题翻译：在电阻变化层和布线层具有共面的非易失性半导体存储器件及其制造方法
公开(公告)号：US08537605B2
公开(公告)日：2013-09-17
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： G11C11/14
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

24. 发明申请

US20130140515A1 NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：US20130140515A1
公开(公告)日：2013-06-06
申请号：US13810840
申请日：2012-02-22
申请人： Yoshio Kawashima , Takumi Mikawa , Ichirou Takahashi
发明人： Yoshio Kawashima , Takumi Mikawa , Ichirou Takahashi
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/1675
摘要： A method of manufacturing a nonvolatile memory element, the method including: forming a first lower electrode layer, a current steering layer, and a first upper electrode layer; forming a second lower electrode layer, a variable resistance layer, and a second upper electrode layer on the first upper electrode layer; patterning the second upper electrode layer, the variable resistance layer, and the lower electrode layer; patterning the first upper electrode layer, the current steering layer, and first lower electrode layer to form a current steering element, using the second lower electrode layer as a mask by use of etching which is performed on the second lower electrode layer at an etching rate lower than at least etching rates at which the second upper electrode layer and the variable resistance layer are etched; and forming a variable resistance element which has an area smaller than the area of the current steering element.
摘要翻译：一种制造非易失性存储元件的方法，所述方法包括：形成第一下电极层，电流引导层和第一上电极层; 在所述第一上电极层上形成第二下电极层，可变电阻层和第二上电极层; 图案化第二上电极层，可变电阻层和下电极层; 对第一上电极层，电流引导层和第一下电极层进行构图，以形成电流导向元件，使用第二下电极层作为掩模，以蚀刻速率在第二下电极层上进行蚀刻低于至少蚀刻第二上电极层和可变电阻层的蚀刻速率; 以及形成面积小于当前操舵元件面积的可变电阻元件。

25. 发明授权

US08389972B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08389972B2
公开(公告)日：2013-03-05
申请号：US13129215
申请日：2010-09-13
申请人： Takumi Mikawa , Yoshio Kawashima
发明人： Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , H01L27/101 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage.The nonvolatile memory device (10) in the present invention includes: a lower electrode (105) formed above a substrate (100); a first variable resistance layer (106a) formed above the lower electrode (105) and comprising a transitional metal oxide; a second variable resistance layer (106b) formed above the first variable resistance layer (106a) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer (106a); and an upper electrode (107) formed above the second variable resistance layer (106b), wherein a step (106ax) is formed in an interface between the first variable is resistance layer (106a) and the second variable resistance layer (106b). The second variable resistance layer (106b) is formed covering the step (106ax) and has a bend (106bx) above the step (106ax).
摘要翻译：通过降低断开电压以实现电阻变化并抑制断开电压的变化来实现存储器的小型化和增加的容量。本发明的非易失性存储器件（10）包括：形成在衬底（100）上方的下电极（105）; 形成在所述下电极（105）上方并且包含过渡金属氧化物的第一可变电阻层（106a）形成在第一可变电阻层（106a）上方的第二可变电阻层（106b），并且包括具有比第一可变电阻层（106a）的过渡金属氧化物高的氧含量的过渡金属氧化物; 以及形成在所述第二可变电阻层（106b）上方的上电极（107），其中在所述第一可变电阻层（106a）和所述第二可变电阻层（106b）之间的界面中形成台阶（106ax）。第二可变电阻层（106b）被形成为覆盖台阶（106ax）并且在台阶（106ax）上方具有弯曲部（106bx）。

26. 发明授权

US08344345B2 Nonvolatile semiconductor memory device having a resistance variable layer and manufacturing method thereof 有权
标题翻译：具有电阻变化层的非易失性半导体存储器件及其制造方法
公开(公告)号：US08344345B2
公开(公告)日：2013-01-01
申请号：US12810667
申请日：2008-12-26
申请人： Takumi Mikawa , Yoshio Kawashima , Ryoko Miyanaga
发明人： Takumi Mikawa , Yoshio Kawashima , Ryoko Miyanaga
IPC分类号： H01L29/02
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).
摘要翻译：包括第一存储器线（12）的第一布线层（19）通过穿过第一层间绝缘层（13）的第一触点（21）连接到包括第二存储器布线（17）的第二布线层（20）。第一导线层（13）经由连接到第二导线层（20）并穿过第二层间绝缘层（18）的第二触点（26）连接并引出到上导线（22）。第一触点（21）穿透第二导线层（20）的半导体层（17b）或绝缘体层（17c）。

27. 发明授权

US09184381B2 Nonvolatile storage element and method for manufacturing same 有权
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：US09184381B2
公开(公告)日：2015-11-10
申请号：US13810800
申请日：2011-10-06
申请人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
发明人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
IPC分类号： H01L47/00 , H01L45/00 , H01L27/10
CPC分类号： H01L45/145 , H01L27/101 , H01L45/08 , H01L45/146 , H01L45/1608 , H01L45/1625
摘要： A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
摘要翻译：可变电阻非易失性存储元件包括：第一电极; 第二电极; 以及可变电阻层，其具有基于施加在所述电极之间的电信号而可逆地变化的电阻值，其中所述可变电阻层具有通过堆叠第一过渡金属氧化物层，第二过渡金属氧化物层和第三过渡金属氧化物层而形成的结构过渡金属氧化物层，第一过渡金属氧化物层具有以MOx表示的组成（其中M是过渡金属，O是氧），第二过渡金属氧化物层具有以MOy表示的组成（其中x> y ）和具有表示为MOz（其中y> z）的组成的第三过渡金属氧化物层。

28. 发明授权

US08889478B2 Method for manufacturing nonvolatile semiconductor memory element, and nonvolatile semiconductor memory element 有权
标题翻译：非易失性半导体存储元件的制造方法及非易失性半导体存储元件
公开(公告)号：US08889478B2
公开(公告)日：2014-11-18
申请号：US13637465
申请日：2011-11-18
申请人： Takumi Mikawa , Yukio Hayakawa , Yoshio Kawashima , Takeki Ninomiya
发明人： Takumi Mikawa , Yukio Hayakawa , Yoshio Kawashima , Takeki Ninomiya
IPC分类号： H01L45/00 , H01L21/8239 , H01L21/02 , H01L27/24 , H01L27/102
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L45/08 , H01L45/146 , H01L45/1675
摘要： Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.
摘要翻译：提供一种用于制造可变电阻非易失性半导体存储元件的方法，以及使得可以在初始击穿时以低电压和高速操作的可变电阻非易失性半导体存储元件，并且表现出良好的二极管元件特性。制造非易失性半导体存储元件的方法包括：在形成可变电阻元件的顶部电极之后，并且至少在形成MSM二极管元件的顶部电极之前，氧化以使可变电阻膜的一部分在一个周围的区域中绝缘可变电阻层的端面。

29. 发明申请

US20140098595A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20140098595A1
公开(公告)日：2014-04-10
申请号：US14122708
申请日：2013-03-27
申请人： Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
发明人： Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/12 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.
摘要翻译：一种非易失性存储器件包括：存储单元阵列，包括多个存储单元，每个存储单元包括第一可变电阻元件和第一电流导引元件;以及参数产生电路，其包括具有第二可变电阻元件和第二电流元件所述转向元件具有与所述第一电流操舵元件相同的电流密度 - 电压特性，其中在所述第二可变电阻元件的侧表面上形成用于在所述电极之间引起短路的导电短路层。

30. 发明申请

US20140024197A1 NONVOLATILE STORAGE ELEMENT AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：非易失存储元件及其制造方法
公开(公告)号：US20140024197A1
公开(公告)日：2014-01-23
申请号：US14110163
申请日：2012-04-11
申请人： Yoshio Kawashima , Takumi Mikawa , Shinichi Imai
发明人： Yoshio Kawashima , Takumi Mikawa , Shinichi Imai
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L27/2436 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A method of manufacturing a variable resistance nonvolatile memory element includes: forming a lower electrode layer above a substrate; forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide; forming an upper electrode layer on the variable resistance layer; and forming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask, wherein in the etching, at least the variable resistance layer is etched using an etching gas containing bromine.
摘要翻译：一种制造可变电阻非易失性存储元件的方法包括：在衬底上形成下电极层; 在下电极层上形成包含缺氧过渡金属氧化物的可变电阻层; 在所述可变电阻层上形成上电极层; 以及在所述上电极层上形成图案化掩模，并使用所述图案掩模蚀刻所述上电极层，所述可变电阻层和所述下电极层，其中在所述蚀刻中，至少所述可变电阻层使用含有溴。

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