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21. 发明申请

US20070084730A1 Plating apparatuses and processes 审中-公开
标题翻译：电镀设备和工艺
公开(公告)号：US20070084730A1
公开(公告)日：2007-04-19
申请号：US11248176
申请日：2005-10-13
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： C25D5/48
CPC分类号： C25D21/00 , C25D5/00 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76877 , H05K3/423
摘要： Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.
摘要翻译：电镀设备和电镀工艺。电镀装置包括电镀站和邻近电镀站的电镀后处理站。电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

22. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

23. 发明申请

US20050250327A1 Copper plating of semiconductor devices using intermediate immersion step 有权
标题翻译：使用中间浸渍步骤的半导体器件的镀铜
公开(公告)号：US20050250327A1
公开(公告)日：2005-11-10
申请号：US10840095
申请日：2004-05-06
申请人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
发明人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
IPC分类号： C25D3/02 , C25D5/10 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/44
CPC分类号： C25D7/123 , C25D3/02 , C25D5/10 , C25D5/18 , H01L21/2885
摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
摘要翻译：在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

24. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

25. 发明授权

US06531382B1 Use of a capping layer to reduce particle evolution during sputter pre-clean procedures 有权
标题翻译：在溅射预清洁过程中使用覆盖层来减少颗粒的发生
公开(公告)号：US06531382B1
公开(公告)日：2003-03-11
申请号：US10140662
申请日：2002-05-08
申请人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
发明人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
IPC分类号： H01L213205
CPC分类号： H01L21/76802 , H01L21/76838
摘要： A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.
摘要翻译：已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

26. 发明申请

US20070205516A1 Low-k dielectric layer, semiconductor device, and method for fabricating the same 审中-公开
标题翻译：低k电介质层，半导体器件及其制造方法
公开(公告)号：US20070205516A1
公开(公告)日：2007-09-06
申请号：US11364088
申请日：2006-03-01
申请人： Kei-Wei Chen , Sheng-Wen Chen , Shiu-Ko Jangjian , Shih-Ho Lin , Hung-Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Sheng-Wen Chen , Shiu-Ko Jangjian , Shih-Ho Lin , Hung-Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/02126 , H01L21/022 , H01L21/0234 , H01L21/3121 , H01L21/3146 , H01L21/31633 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.
摘要翻译：低k电介质层，半导体器件及其制造方法。低k电介质层包括夹在两个低k电介质子层之间的硬化子层。硬化的子层通过利用氢等离子体或惰性气体等离子体轰击下面的低k电介质子层的方法形成。半导体器件包括覆盖衬底上的蚀刻停止层的低k电介质层，以及电连接到衬底的埋入电介质层和蚀刻停止层中的导电材料。

27. 发明授权

US06769959B2 Method and system for slurry usage reduction in chemical mechanical polishing 失效
标题翻译：化学机械抛光中浆料用量减少的方法和系统
公开(公告)号：US06769959B2
公开(公告)日：2004-08-03
申请号：US10050314
申请日：2002-01-15
申请人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
发明人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
IPC分类号： B24B100
CPC分类号： B24B37/04 , B24B57/02
摘要： A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.
摘要翻译：公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。浆料可以间歇地供应到化学机械抛光装置。通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

28. 发明授权

US06248002B1 Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish 有权
标题翻译：通过在浆液抛光后在更软的垫上添加浆料抛光，获得熔融CMP工艺的更好的缺陷性能
公开(公告)号：US06248002B1
公开(公告)日：2001-06-19
申请号：US09421509
申请日：1999-10-20
申请人： Hui-Ling Wang , Tong-Hua Kuan , Ying-Lang Wang , Yu-Ku Lin
发明人： Hui-Ling Wang , Tong-Hua Kuan , Ying-Lang Wang , Yu-Ku Lin
IPC分类号： B24B100
CPC分类号： B24B37/042
摘要： A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.
摘要翻译：一种在抛光晶片表面的过程中防止颗粒杂质在含有钨骨塞的半导体衬底表面积聚的方法。抛光顺序由三个不同的抛光步骤组成，其中前两个步骤使用硬抛光垫，而第三步在第三次抛光期间使用软抛光垫施加浆料。

29. 发明授权

US07955993B2 Oxygen plasma reduction to eliminate precursor overflow in BPTEOS film deposition 有权
标题翻译：氧气等离子体还原以消除BPTEOS薄膜沉积中的前体溢出
公开(公告)号：US07955993B2
公开(公告)日：2011-06-07
申请号：US12478493
申请日：2009-06-04
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L21/0234 , H01L21/3105 , H01L21/76826
摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
摘要翻译：一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和硼掺杂剂富含膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

30. 发明申请

US20100311252A1 OXYGEN PLASMA REDUCTION TO ELIMINATE PRECURSOR OVERFLOW IN BPTEOS FILM DEPOSITION 有权
标题翻译：消除BPTEOS膜沉积中前体溢出的氧气等离子体减少
公开(公告)号：US20100311252A1
公开(公告)日：2010-12-09
申请号：US12478493
申请日：2009-06-04
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/283 , H01L21/285
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L21/0234 , H01L21/3105 , H01L21/76826
摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
摘要翻译：一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和富含硼的掺杂剂的膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

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