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21. 发明授权

US4164791A Semiconductor memory with equal word line and reference line voltage drop 失效
标题翻译：具有相等字线和参考线电压降的半导体存储器
公开(公告)号：US4164791A
公开(公告)日：1979-08-14
申请号：US860092
申请日：1977-12-13
申请人： Noriyuki Homma
发明人： Noriyuki Homma
IPC分类号： G11C11/41 , G11C5/06 , G11C11/411 , G11C11/414 , G11C11/415 , G11C11/416 , H01L21/822 , H01L27/04 , H01L27/10 , H03K19/00 , G11C7/00 , G11C11/40
CPC分类号： G11C5/063 , G11C11/4116 , G11C11/415 , G11C11/416
摘要： A semiconductor memory includes a plurality of memory cells connected between word line pairs and between the digit line pairs in matrix form. To compensate for voltage drops developed along the word line, there are provided current sources, each of which is connected to a reference line to supply constant currents equal in value to the current flowing through the word line. Moreover, another current source is connected to a word addressing voltage drive circuit to compensate for voltage drops developed along the digit line.
摘要翻译：半导体存储器包括以矩阵形式连接在字线对之间和数字线对之间的多个存储器单元。为了补偿沿着字线发展的电压降，提供了电流源，每个电流源连接到参考线，以提供与流过字线的电流值相等的恒定电流。此外，另一电流源连接到字寻址电压驱动电路以补偿沿数字线发展的电压降。

22. 发明授权

US4156941A High speed semiconductor memory 失效
标题翻译：高速半导体存储器
公开(公告)号：US4156941A
公开(公告)日：1979-05-29
申请号：US836969
申请日：1977-09-27
申请人： Noriyuki Homma , Kunihiko Yamaguchi
发明人： Noriyuki Homma , Kunihiko Yamaguchi
IPC分类号： G11C11/41 , G11C11/414 , G11C11/415 , G11C11/416 , H03K17/00 , G11C11/40 , G11C13/00
CPC分类号： G11C11/416 , G11C11/415
摘要： A semiconductor memory capable of being operated at high speed is disclosed. Each memory cell consists of a pair of cross-coupled transistors connected between two word lines. Application of the read or write pulse to one of the word lines is detected and the signal thus detected is applied to a delay circuit. The output of the delay circuit is applied to a current switch transistor connected to the other word line for turning it on during the predetermined period of time at least just after the reading or writing cycle of the selected cell, thereby quickly clamping the word lines to the predetermined potentials.
摘要翻译：公开了能够高速运转的半导体存储器。每个存储单元由连接在两个字线之间的一对交叉耦合晶体管组成。读取或写入脉冲到一行字线的检测，将这样检测的信号施加到延迟电路上。延迟电路的输出被施加到连接到另一个字线的电流开关晶体管，用于在至少刚好在所选择的单元的读取或写入周期之后的预定时间段期间将其导通，从而快速地将字线夹紧到预定电位。

23. 发明授权

US06740958B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06740958B2
公开(公告)日：2004-05-25
申请号：US10115101
申请日：2002-04-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L2900
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

24. 发明授权

US5386135A Semiconductor CMOS memory device with separately biased wells 失效
标题翻译：半导体CMOS存储器件具有单独偏置的阱
公开(公告)号：US5386135A
公开(公告)日：1995-01-31
申请号：US229340
申请日：1994-04-12
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

25. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

26. 发明授权

US5148255A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5148255A
公开(公告)日：1992-09-15
申请号：US645351
申请日：1991-01-23
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

27. 发明授权

US4928265A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4928265A
公开(公告)日：1990-05-22
申请号：US266148
申请日：1988-11-02
申请人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
发明人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
摘要翻译：考虑到半导体存储器的访问时间的偏差，至少第一和第二存储器电路连接到读出放大器的输出。读出放大器的输出是以不同的定时交替地输入到这两个存储器电路。存储在这些存储器电路中的数据被交替地传送到数据输出电路。即使当访问时间变长时，可以在由时钟周期确定的短时间间隔内从数据输出电路的输出端连续地读出期望的感测数据。当访问时间变短时，即使在将第一存储器电路中的第一数据传送到数据输出电路的定时从读出放大器的输出产生第二数据时，保持在第一存储器电路中的第一数据为防止第二个数据被更新。在这种情况下，也可以在由时钟周期确定的时间间隔内从数据输出电路的输出端连续读出期望的检测数据。

28. 发明授权

US4905078A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4905078A
公开(公告)日：1990-02-27
申请号：US84074
申请日：1987-08-11
申请人： Kazuhiko Sagara , Yoichi Tamaki , Noriyuki Homma , Tohru Nakamura
发明人： Kazuhiko Sagara , Yoichi Tamaki , Noriyuki Homma , Tohru Nakamura
IPC分类号： G11C11/411 , H01L21/8229 , H01L27/102
CPC分类号： H01L27/1025 , Y10S257/906 , Y10S257/926
摘要： A semiconductor device includes a semiconductor layer provided above a pair of bipolar transistors formed in a surface region of a semiconductor body. Schottky barrier diodes and resistors are formed in the semiconductor layer. The pair of bipolar transistors, the Schottky barrier diodes and the resistors are electrically connected to constitute a bipolar memory. Since the Schottky barrier diodes and the resistors can be formed above the bipolar transistors, an area required for the memory cell can be made greatly small and the occurrence of an hindrance caused by .alpha. particles is minimal.
摘要翻译：半导体器件包括设置在形成在半导体本体的表面区域中的一对双极晶体管之上的半导体层。在半导体层中形成肖特基势垒二极管和电阻。一对双极晶体管，肖特基势垒二极管和电阻器电连接以构成双极存储器。由于肖特基势垒二极管和电阻器可以形成在双极晶体管的上方，所以可以使存储单元所需的面积变得非常小，并且由α粒子引起的阻碍的发生是最小的。

29. 发明授权

US4866673A BI-MOS semiconductor memory having high soft error immunity 失效
标题翻译：具有高软错误抗扰度的BI-MOS半导体存储器
公开(公告)号：US4866673A
公开(公告)日：1989-09-12
申请号：US38940
申请日：1987-04-16
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
IPC分类号： G11C11/41 , G11C11/416 , G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C11/419
摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by .alpha. rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
摘要翻译：提供具有高可靠性的半导体存储器，并且特别地防止由α射线引起的数据破坏等。在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载的数据线。字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

30. 发明授权

US4812894A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4812894A
公开(公告)日：1989-03-14
申请号：US191761
申请日：1988-05-03
申请人： Tohru Nakamura , Kazuo Nakazato , Noriyuki Homma , Kazuhiko Sagara , Takeo Shiba , Tokuo Kure , Tetsuya Hayashida
发明人： Tohru Nakamura , Kazuo Nakazato , Noriyuki Homma , Kazuhiko Sagara , Takeo Shiba , Tokuo Kure , Tetsuya Hayashida
IPC分类号： H01L29/73 , H01L21/331 , H01L21/337 , H01L21/822 , H01L23/485 , H01L27/04 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/732 , H01L29/808 , H01L29/06
CPC分类号： H01L29/66272 , H01L23/485 , H01L27/0658 , H01L29/0804 , H01L29/0808 , H01L29/1004 , H01L29/41 , H01L29/41708 , H01L29/42304 , H01L29/42316 , H01L29/8083 , H01L2924/0002
摘要： A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.
摘要翻译：半导体器件包括形成在单晶衬底上并具有开口的第一绝缘膜，形成为突出到第一绝缘膜中的单晶半导体层和与单晶半导体层的侧部接触形成的导电层，以及在形成在单晶半导体层上的第二绝缘膜上延伸。

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