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21. 发明授权

US08451648B2 Resistance-change memory and method of operating the same 有权
标题翻译：电阻变化记忆及其操作方法
公开(公告)号：US08451648B2
公开(公告)日：2013-05-28
申请号：US13181949
申请日：2011-07-13
申请人： Masahiro Kamoshida , Katsuaki Sakurai , Takahiko Sasaki
发明人： Masahiro Kamoshida , Katsuaki Sakurai , Takahiko Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0092 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude, and a control circuit which controls the operations of the memory element and the pulse generation circuit. The control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element.
摘要翻译：根据一个实施例，电阻变化存储器包括其可变电阻状态对应于要存储的数据的存储元件，产生第一脉冲，第二脉冲，第三脉冲和第四脉冲的脉冲产生电路所述第一脉冲具有将所述存储元件的电阻状态从高电阻状态改变为低电阻状态的第一幅度，所述第三脉冲具有小于所述第一幅度的第三幅度以读取所述存储元件中的数据，所述第四脉冲具有第一幅度和第三幅度之间的第四幅度的脉冲，以及控制存储元件和脉冲发生电路的操作的控制电路。控制电路在将第一脉冲提供给存储元件之后将第四脉冲提供给存储元件。

22. 发明申请

US20120149611A1 Coating Composition For Sliding Members 审中-公开
标题翻译：用于滑动构件的涂料组合物
公开(公告)号：US20120149611A1
公开(公告)日：2012-06-14
申请号：US13391308
申请日：2010-08-19
申请人： Tetsuji Yamaguchi , Takahiko Sasaki
发明人： Tetsuji Yamaguchi , Takahiko Sasaki
IPC分类号： C10M155/02
CPC分类号： C08J7/047 , C08J2321/00 , C08J2483/00 , C08L83/04 , C09D7/61 , C09D175/04 , C09D175/06 , C10M107/00 , C10M107/50 , C10M2205/0206 , C10M2209/0845 , C10M2215/14 , C10M2217/0453 , C10M2229/02 , C10M2229/025 , C10N2220/022 , C10N2230/06 , C10N2250/121 , C08L75/04 , C08L23/00
摘要： A coating composition for a sliding member, wherein from 30 to 120 parts by weight of a solid lubricant and from 5 to 80 parts by weight of a silicone resin are included per 100 parts by weight of a film-forming organic resin. As a result of forming the film on the surface of the sliding member, a coating composition for a sliding member is provided whereby low frictional drag can be maintained for an extended period of time, and the sticking of the sliding member to glass surfaces and similar smooth surfaces can be prevented.
摘要翻译：包含每100重量份成膜有机树脂的滑动构件用涂料组合物，其中30至120重量份的固体润滑剂和5至80重量份的有机硅树脂。作为在滑动构件的表面上形成薄膜的结果，提供了一种用于滑动构件的涂料组合物，其中可以长时间保持低摩擦阻力，并且将滑动构件粘附到玻璃表面和类似物可以防止光滑的表面。

23. 发明申请

US20110141794A1 SEMICONDUCTOR MEMORY DEVICE AND INSPECTING METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US20110141794A1
公开(公告)日：2011-06-16
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C29/02 , G11C11/21
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

24. 发明申请

US20090147561A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20090147561A1
公开(公告)日：2009-06-11
申请号：US12328637
申请日：2008-12-04
申请人： Takahiko Sasaki , Atsushi Kawasumi
发明人： Takahiko Sasaki , Atsushi Kawasumi
IPC分类号： G11C11/00 , G11C11/416 , G11C7/00
CPC分类号： G11C7/18 , G11C5/025 , G11C11/412 , G11C11/413
摘要： A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any one of the pair of bit lines. A write circuit is arranged, separately from the read circuit, at the other side of the memory cell array. The write circuit provides written data to the pair of bit lines to write data to the SRAM cells.
摘要翻译：半导体存储装置包括具有沿着沿第一方向延伸的一对位线布置的多个SRAM单元的存储单元阵列。为存储单元阵列的一侧的每列配置读取电路，并且检测该对位线中的任何一个的电位。写入电路与读取电路分开地布置在存储单元阵列的另一侧。写电路将写数据提供给该对位线，以将数据写入SRAM单元。

25. 发明申请

US20090067222A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090067222A1
公开(公告)日：2009-03-12
申请号：US12207949
申请日：2008-09-10
申请人： Atsushi KAWASUMI , Takahiko Sasaki
发明人： Atsushi KAWASUMI , Takahiko Sasaki
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor.
摘要翻译： SRAM单元沿着第一和第二位线和用于单端读取第二位线的数据的字线被排列成矩阵。包含在SRAM单元中的第一NMOS晶体管和第一传输晶体管形成在具有相同的栅极长度和栅极宽度的第一阱中。包含在SRAM单元中的第二NMOS晶体管和第二传输晶体管形成在具有各自相同的栅极长度和栅极宽度的第二阱中。这些栅极宽度比第一NMOS晶体管和第一转移晶体管的栅极宽度宽。

26. 发明授权

US07368801B2 Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same 有权
标题翻译：半导体电可编程熔丝元件与非晶硅层编程及编程方法相同
公开(公告)号：US07368801B2
公开(公告)日：2008-05-06
申请号：US10851143
申请日：2004-05-24
申请人： Nobuaki Otsuka , Takahiko Sasaki , Shuso Fujii
发明人： Nobuaki Otsuka , Takahiko Sasaki , Shuso Fujii
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
摘要翻译：在第一和第二端子之间形成熔丝连接。第一和第二端子和熔丝链路具有多晶硅层和形成在多晶硅层上并且包含金属元件的层。熔丝链的至少一部分是非晶硅层。

27. 发明授权

US08730745B2 Semiconductor device and method for controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08730745B2
公开(公告)日：2014-05-20
申请号：US13428256
申请日：2012-03-23
申请人： Takahiko Sasaki
发明人： Takahiko Sasaki
IPC分类号： G11C5/14
CPC分类号： G11C5/025 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C2213/71
摘要： According to one embodiment, a semiconductor memory device includes a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction, a plurality of second interconnects which extend in the second direction and are arranged in the first direction, and a plurality of first storage modules which are formed in regions where the first interconnects and the second interconnects cross. The semiconductor memory device further comprises a first interconnect control module which supplies a voltage to the first interconnects, detects a first current flowing in the first interconnects, and outputs a first voltage corresponding to the first current, a reference voltage generator module which generates a second voltage based on a second current, and a regulator which generates a third voltage based on the first voltage and the second voltage.
摘要翻译：根据一个实施例，半导体存储器件包括多个第一互连件，它们在第一方向上延伸并且沿垂直于第一方向的第二方向布置;多个第二互连件，其在第二方向上延伸并布置在第一方向和多个第一存储模块，其形成在第一互连和第二互连交叉的区域中。半导体存储器件还包括第一互连控制模块，其向第一互连提供电压，检测在第一互连中流动的第一电流，并输出与第一电流对应的第一电压;参考电压发生器模块，其产生第二互连基于第二电流的电压，以及基于第一电压和第二电压产生第三电压的调节器。

28. 发明授权

US08503255B2 Semiconductor storage device including plural clock oscillator circuits operating at different frequencies 有权
标题翻译：半导体存储装置包括以不同频率工作的多个时钟振荡器电路
公开(公告)号：US08503255B2
公开(公告)日：2013-08-06
申请号：US12818678
申请日：2010-06-18
申请人： Takahiko Sasaki
发明人： Takahiko Sasaki
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C5/145 , G11C13/0007 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2213/71
摘要： According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The memory cell array has memory cells arranged therein at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a variable resistance element. The control circuit is configured to apply a voltage to a selected one of the first wirings and to a selected one of the second wirings. The control circuit includes a plurality of charge pump circuits and a plurality of clock oscillator circuits. The charge pump circuits generate a voltage applied to the first and second wirings. Each of the clock oscillator circuits is configured to supply a clock signal to a certain number of the charge pump circuits to control the timing of operation thereof. The clock oscillator circuits are configured to output clock signals at different frequencies.
摘要翻译：根据一个实施例，半导体存储装置包括存储单元阵列和控制电路。存储单元阵列具有在多个第一布线和多个第二布线之间的相应交点处布置有存储单元的存储单元。每个存储单元具有可变电阻元件。控制电路被配置为对所选择的第一布线中的一个和所选择的第二布线施加电压。控制电路包括多个电荷泵电路和多个时钟振荡器电路。电荷泵电路产生施加到第一和第二布线的电压。每个时钟振荡器电路被配置为向一定数量的电荷泵电路提供时钟信号以控制其操作的定时。时钟振荡器电路被配置为以不同的频率输出时钟信号。

29. 发明授权

US08493770B2 Non-volatile semiconductor storage device with concurrent read operation 有权
标题翻译：具有并发读取操作的非易失性半导体存储器件
公开(公告)号：US08493770B2
公开(公告)日：2013-07-23
申请号：US12884965
申请日：2010-09-17
申请人： Koji Hosono , Yuri Terada , Takahiko Sasaki
发明人： Koji Hosono , Yuri Terada , Takahiko Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C7/1015
摘要： A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.
摘要翻译：半导体存储装置包括存储单元阵列，该存储单元阵列包括布置在第一布线和第二布线之间的相应交点处的存储单元。每个存储单元包括串联连接的整流元件和可变电阻元件。控制电路被配置为将第一电压施加到所选择的第一布线和低于第一电压的第二电压到所选择的第二布线，使得某一电位差被施加到位于所选择的第一布线之间的交叉点处的选定存储单元接线和选定的第二个接线。控制电路通过同时向多个第一布线施加第一电压来执行同时读取操作，以同时从多个存储单元执行读取操作。可以在同时读取操作中同时切换要应用第一电压的第一布线的数量。

30. 发明授权

US08264867B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08264867B2
公开(公告)日：2012-09-11
申请号：US12885881
申请日：2010-09-20
申请人： Kazuaki Kawaguchi , Takahiko Sasaki , Tomonori Kurosawa
发明人： Kazuaki Kawaguchi , Takahiko Sasaki , Tomonori Kurosawa
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C2013/0083
摘要： According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.
摘要翻译：根据一个实施例，具有多个操作模式的非易失性半导体存储装置包括：多个第一线; 多条第二线; 多个存储单元; 第一选择单元，将第一行充电到第一选择电压; 以及第二选择单元，其在第一线路被第一选择单元充电到第一选择电压之后，将第二线路充电到非选择电压并将第二线路放电到第二选择电压，其中第二选择单元调整至少一个根据非易失性半导体存储装置在多个操作中的操作模式，要选择要选择的第二线路的第二选择电压的电平和放电要选择的第二线路的时间常数的操作模式。

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