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21. 发明授权

US6026034A Bit line reset circuit of memory 失效
标题翻译：存储器的位线复位电路
公开(公告)号：US6026034A
公开(公告)日：2000-02-15
申请号：US73928
申请日：1998-05-07
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C11/407 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4094 , G11C7/12
摘要： Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.
摘要翻译：开关晶体管20,22,22P，21,23和23P以及用于晶体管20和21的控制电路的一部分构成存储单元侧的位线复位电路。在从连接到位线BLC或* BLC的存储单元读取“H”时，两个位线都被设置在较高的复位电位Vii，而在读取“L”时，两个位线都以较低的复位电位复位 Vss。在充分放大位线BL和* BL之间的电位差之前，转移门10和11被截止。与位线复位的操作并行执行从存储单元中恢复读取的操作。

22. 发明授权

US06721910B2 Semiconductor memory improved for testing 有权
标题翻译：半导体存储器改进了测试
公开(公告)号：US06721910B2
公开(公告)日：2004-04-13
申请号：US09400831
申请日：1999-09-21
申请人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
发明人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C2900
CPC分类号： G11C5/063 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, the transmission time of a control signal is tested by connecting various combinations of the capacitors to the signal wire, and then measuring the signal timing. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.
摘要翻译：同步DRAM（SDRAM）或快速周期RAM（FCRAM）包括通过开关连接到信号线的电容器。控制开关将电容器连接到信号线。在测试模式下，通过将各种电容器的组合连接到信号线，然后测量信号时序来测试控制信号的传输时间。可以通过选择哪个和多少电容器连接到信号线来控制存储器件的信号定时。

23. 发明授权

US06353561B1 Semiconductor integrated circuit and method for controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06353561B1
公开(公告)日：2002-03-05
申请号：US09397845
申请日：1999-09-17
申请人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
发明人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.
摘要翻译：诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。这允许在外部时钟的每个周期获取多于一个外部命令。获取的外部命令被提供给命令解码器进行解码。当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

24. 发明授权

US6108243A High-speed random access memory device 有权
标题翻译：高速随机存取存储器
公开(公告)号：US6108243A
公开(公告)日：2000-08-22
申请号：US383014
申请日：1999-08-25
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.
摘要翻译：本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

25. 发明授权

US06301173B2 Memory device with faster reset operation 有权
标题翻译：具有更快复位操作的存储器件
公开(公告)号：US06301173B2
公开(公告)日：2001-10-09
申请号：US09307758
申请日：1999-05-10
申请人： Shinya Fujioka , Yasuharu Sato
发明人： Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C7/12
摘要： The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs. According to the above structure, the reset operation involving a bit line short operation can be executed at high-speed, since the bit line short circuit is disposed for each bit line pair. Also area efficiency can be improved since the bit line clamper circuit is shared by the first and the second bit line pairs.
摘要翻译：本发明是具有多个字线，多个位线对和设置在其交叉位置的存储单元的存储电路。存储器包括：读出放大器，由第一位线对和位于列方向上的第二位线对共享，并放大位线对的电压; 第一位线传输门和第二位线传输门，其布置在读出放大器与第一和第二位线对之间，并将所选存储单元侧的位线对连接到读出放大器; 位于第一和第二位线传输门之间的位线钳位器由第一位线对和第二位线对共用，并将预充电电平提供给位线对; 以及分别布置在第一和第二位线对上并使位线对短路的位线短路。根据上述结构，由于对每个位线对设置位线短路，所以可以高速执行涉及位线短路操作的复位动作。由于位线钳位电路由第一位线对和第二位线对共享，所以可以提高面积效率。

26. 发明授权

US06324111B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06324111B1
公开(公告)日：2001-11-27
申请号：US09561217
申请日：2000-04-28
申请人： Yasuharu Sato , Shinya Fujioka
发明人： Yasuharu Sato , Shinya Fujioka
IPC分类号： G11C702
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A semiconductor memory includes p-type MOS transistors (11) dispersed in one-to-one correspondence with sense amplifiers (4−1-4−n) to activate their corresponding sense amplifiers, and a p-type MOS transistor (12) to activate the sense amplifiers (4−1-4−n). After the p-type MOS transistors (11) are overdriven by an external voltage (VCC) higher than a memory stored voltage, the p-type MOS transistor (12) is driven by an internal step-down voltage (VII) that is the memory stored voltage. This increases the driving capability per sense amplifier in comparison with a conventional method and further increases the speed of sense operation in comparison with a simple overdriving method.
摘要翻译：半导体存储器包括与读出放大器（4-1-4-n）一一对应地分散以激活其对应的读出放大器的p型MOS晶体管（11），以及p型MOS晶体管（12），激活读出放大器（4-1-4-n）。在p型MOS晶体管（11）被高于存储器存储电压的外部电压（VCC）驱动之后，p型MOS晶体管（12）由内部降压电压（VII）驱动，存储电压。与传统方法相比，这增加了每个读出放大器的驱动能力，并且与简单的过驱动方法相比进一步增加了感测操作的速度。

27. 发明授权

US6084823A Synchronous semiconductor memory device and bus control method 有权
标题翻译：同步半导体存储器件和总线控制方法
公开(公告)号：US6084823A
公开(公告)日：2000-07-04
申请号：US323852
申请日：1999-06-02
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1072
摘要： There is provided a semiconductor integrated circuit memory comprising banks each having at least one memory cell array and connected to a first data bus. Each of the banks includes a control part which is supplied with information indicated by a command and thus controls a data write or read operation on a corresponding bank. The control part controls data write and read operations on the corresponding bank so that the corresponding bank is prevented from occupying the first data bus until read data is output to the first data bus by the data read operation.
摘要翻译：提供了包括各自具有至少一个存储单元阵列并连接到第一数据总线的存储体的半导体集成电路存储器。每个存储体包括控制部分，其被提供有由命令指示的信息，并且因此控制相应存储体上的数据写入或读取操作。控制部分控制对应的存储体上的数据写入和读取操作，以便通过数据读取操作将读取数据输出到第一数据总线之前，防止对应的存储体占用第一数据总线。

28. 发明授权

US06961830B2 Semiconductor memory device with fast masking process in burst write mode 失效
标题翻译：具有突发写入模式的快速掩蔽处理的半导体存储器件
公开(公告)号：US06961830B2
公开(公告)日：2005-11-01
申请号：US10327096
申请日：2002-12-24
申请人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
发明人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/28
CPC分类号： G11C7/22 , G11C7/1006 , G11C2207/229
摘要： A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
摘要翻译：半导体存储器件具有突发写入模式，其中通过多个命令焊盘输入预定的多个命令信号，并且响应于命令信号执行脉冲串写入模式中的掩码控制操作。因此，突发写入模式中的掩码控制的速度提高，从而提高数据传输速率。

29. 发明授权

US06535965B1 Semiconductor memory device with fast masking process in burst write mode 有权
标题翻译：具有突发写入模式的快速掩蔽处理的半导体存储器件
公开(公告)号：US06535965B1
公开(公告)日：2003-03-18
申请号：US09559099
申请日：2000-04-27
申请人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
发明人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1006 , G11C2207/229
摘要： A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
摘要翻译：半导体存储器件具有突发写入模式，其中通过多个命令焊盘输入预定的多个命令信号，并且响应于命令信号执行脉冲串写入模式中的掩码控制操作。因此，突发写入模式中的掩码控制的速度提高，从而提高数据传输速率。

30. 发明授权

US08154710B2 Lithography process window analyzing method and analyzing program 失效
标题翻译：光刻过程窗口分析方法和分析程序
公开(公告)号：US08154710B2
公开(公告)日：2012-04-10
申请号：US12400677
申请日：2009-03-09
申请人： Shoji Mimotogi , Yasuharu Sato
发明人： Shoji Mimotogi , Yasuharu Sato
IPC分类号： G03B27/32 , G03B27/52
CPC分类号： G03B27/32 , G03F7/705
摘要： A lithography process window analyzing method for setting a process window based on ranges of exposure amounts and focus positions, and giving evaluation of reliability of the set process window, includes setting, based on a plurality of process conditions including exposure amounts and focus positions in the performed exposure processing, analysis reliability M for process conditions including an arbitrary exposure amount and an arbitrary focus position; calculating reliability R of the process window based on the analysis reliability M concerning the process conditions included in the process window; and comparing a magnitude relation between the reliability R and a predetermined threshold and determining presence or absence of reliability of the process window according to a result of the comparison.
摘要翻译：一种用于基于曝光量和焦点位置的范围来设置处理窗口的光刻处理窗口分析方法，以及对设置的处理窗口的可靠性的评估，包括基于多个处理条件，包括曝光量和焦点位置执行曝光处理，包括任意曝光量和任意焦点位置的处理条件的分析可靠度M; 基于与处理窗口中包含的处理条件有关的分析可靠度M来计算处理窗口的可靠度R; 以及根据比较结果比较可靠度R和预定阈值之间的大小关系，并确定处理窗口的可靠性的存在与否。

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