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21. 发明授权

US08428195B2 Methods and apparatus for detecting and decoding adaptive equalization training frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US08428195B2
公开(公告)日：2013-04-23
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/06
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

22. 发明申请

US20060192593A1 Method and apparatus for continuous-averaging counter-based digital frequency lock detector 有权
标题翻译：基于数字频率锁定检测器的连续平均方法和装置
公开(公告)号：US20060192593A1
公开(公告)日：2006-08-31
申请号：US11068225
申请日：2005-02-28
申请人： Xingdong Dai
发明人： Xingdong Dai
IPC分类号： H03D13/00
CPC分类号： H03L7/095 , H04J3/0685
摘要： Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is less than a number of bits of the reference counter. A frequency offset violation of the target clock is detected by comparing a value of the target counter to an n bit counter.
摘要翻译：提供了基于反数字频率锁定检测的方法和装置。根据本发明的基于计数器的数字频率锁定检测器包括由参考时钟计时的参考计数器和由目标时钟计时的目标计数器。目标计数器是n位，n小于参考计数器的位数。通过将目标计数器的值与n位计数器进行比较来检测目标时钟的频偏偏移。

23. 发明授权

US06377086B1 Low power dual-voltage sense circuit buffer 有权
标题翻译：低功率双电压检测电路缓冲器
公开(公告)号：US06377086B1
公开(公告)日：2002-04-23
申请号：US09412491
申请日：1999-10-05
申请人： Laurence E. Bays , Dennis A. Brooks , Xingdong Dai , Richard Muscavage
发明人： Laurence E. Bays , Dennis A. Brooks , Xingdong Dai , Richard Muscavage
IPC分类号： H03B100
CPC分类号： H03K19/018521
摘要： A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.
摘要翻译：设计用于混合电压系统的全静态双电压检测电路可以感测到器件接口的其他器件的电源电压，并且在感测电路处于活动状态时，无需软件辅助即可实现低功耗级别，并保护电路中的低压工艺装置免受接口处的高压损坏。在优选实施例中，本发明包括具有双电压检测电路的集成电路，感测电路包括提供有输入电压Vin的感测电路输入节点; 提供有电源电压的感测电路电力输入节点; 以及感测电路输出节点，输出等于或小于低电压数字信号的电压电平的电压电平的数字信号，而与输入电压的电压电平无关。

24. 发明授权

US07714667B2 Programmable linear trimming method and system for phase locked loop circuit calibration 失效
标题翻译：用于锁相环电路校准的可编程线性微调方法和系统
公开(公告)号：US07714667B2
公开(公告)日：2010-05-11
申请号：US11934426
申请日：2007-11-02
申请人： Xingdong Dai , Yasser Ahmed , Christopher J. Abel , Shawn Michael Logan
发明人： Xingdong Dai , Yasser Ahmed , Christopher J. Abel , Shawn Michael Logan
IPC分类号： H03L7/113
CPC分类号： H03L7/18 , H03L7/087 , H03L7/095 , H03L2207/06
摘要： The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.
摘要翻译：本发明实现了一种用于校准锁相环（PLL）电路的装置。该装置包括用于检测PLL电路中包含的参考信号和受控振荡器的频率的检测器。检测器将频差输出到控制电路。控制电路被编程为基于有序的频率差来调整一个或多个控制信号到受控振荡器以完成校准过程。

25. 发明申请

US20090175395A1 DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO 有权
标题翻译：具有可编程内容描述信息的仲裁输入的数据对齐方法
公开(公告)号：US20090175395A1
公开(公告)日：2009-07-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

26. 发明申请

US20090115536A1 PROGRAMMABLE LINEAR TRIMMING METHOD AND SYSTEM FOR PHASE LOCKED LOOP CIRCUIT CALIBRATION 失效
标题翻译：可编程线性修正方法和系统，用于相位锁定环路校准
公开(公告)号：US20090115536A1
公开(公告)日：2009-05-07
申请号：US11934426
申请日：2007-11-02
申请人： Xingdong Dai , Yasser Ahmed , Christopher J. Abel , Shawn Michael Logan
发明人： Xingdong Dai , Yasser Ahmed , Christopher J. Abel , Shawn Michael Logan
IPC分类号： H03L7/099 , G01R23/00
CPC分类号： H03L7/18 , H03L7/087 , H03L7/095 , H03L2207/06
摘要： The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.
摘要翻译：本发明实现了一种用于校准锁相环（PLL）电路的装置。该装置包括用于检测PLL电路中包含的参考信号和受控振荡器的频率的检测器。检测器将频差输出到控制电路。控制电路被编程为基于有序的频率差来调整一个或多个控制信号到受控振荡器以完成校准过程。

27. 发明授权

US06282666B1 Computer peripheral device having the capability to wake up from a cold state with information stored before cold powerdown 有权
标题翻译：计算机外围设备具有从冷启动状态存储的信息从冷态唤醒的能力
公开(公告)号：US06282666B1
公开(公告)日：2001-08-28
申请号：US09257954
申请日：1999-02-26
申请人： Laurence Edward Bays , Richard Muscavage , Dennis A. Brooks , Xingdong Dai , Eric Wilcox
发明人： Laurence Edward Bays , Richard Muscavage , Dennis A. Brooks , Xingdong Dai , Eric Wilcox
IPC分类号： G06F1202
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： A computer peripheral device suitable for operation with a Peripheral Component Interconnect (PCI) Bus or the like, has the ability to “wakeup” the bus from a cold state (e.g., D3cold) without the need to supply auxiliary power (e.g., 3.3 volts) to the entire device during the cold state. A modem in the preferred embodiment (although the invention is applicable to other peripheral devices), the device latches device status information from the main circuitry of the device (operating on 5 volts, for example) into a “keep alive” circuit connected to the auxiliary power supply upon the falling edge of a PCI reset signal (RST#). Additionally, the auxiliary power supply also powers a ring detect circuit for the detection of an incoming telephone call, which incoming call triggers a Power Management Event (PME#) signal for changing the state of the bus to an active state. Further, the auxiliary power supply powers a RST# detection circuit for indicating that a change in the power state of the bus is imminent.
摘要翻译：适用于使用外围组件互连（PCI）总线等的计算机外围设备具有从总线“冷却”（例如，D3cold）唤醒总线的能力，而不需要提供辅助电源（例如，3.3伏特）在冷态期间到整个设备。在优选实施例中的调制解调器（尽管本发明可应用于其他外围设备），设备将来自设备的主电路（例如，在5伏特上工作）的设备状态信息锁定到连接到辅助电源在PCI复位信号（RST＃）的下降沿。此外，辅助电源还为环路检测电路供电以检测进入的电话呼叫，该来电呼叫触发电力管理事件（PME＃）信号，以将总线的状态改变为活动状态。此外，辅助电源为RST＃检测电路供电，用于指示总线的功率状态的改变即将到来。

28. 发明授权

US08717067B2 Method and apparatus for continuous-averaging counter-based digital frequency lock detector 有权
标题翻译：基于数字频率锁定检测器的连续平均方法和装置
公开(公告)号：US08717067B2
公开(公告)日：2014-05-06
申请号：US11068225
申请日：2005-02-28
申请人： Xingdong Dai
发明人： Xingdong Dai
IPC分类号： H03D13/00
CPC分类号： H03L7/095 , H04J3/0685
摘要： Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is less than a number of bits of the reference counter. A frequency offset violation of the target clock is detected by comparing a value of the target counter to an n bit counter.
摘要翻译：提供了基于反数字频率锁定检测的方法和装置。根据本发明的基于计数器的数字频率锁定检测器包括由参考时钟计时的参考计数器和由目标时钟计时的目标计数器。目标计数器是n位，n小于参考计数器的位数。通过将目标计数器的值与n位计数器进行比较来检测目标时钟的频偏偏移。

29. 发明授权

US08699550B2 Phase alignment between phase-skewed clock domains 有权
标题翻译：相位偏移时钟域之间的相位对准
公开(公告)号：US08699550B2
公开(公告)日：2014-04-15
申请号：US13425467
申请日：2012-03-21
申请人： Yasser Ahmed , Xingdong Dai
发明人： Yasser Ahmed , Xingdong Dai
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L7/02 , H04L7/0337
摘要： In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.
摘要翻译：为了补偿具有不同同步时钟域的不同电路组之间的相位偏移，一个域的发射（TX）电路被配置为发送模式信号（例如，伪随机位序列）以接收（RX）电路其他域名 RX电路循环许多不同的相移RX时钟信号，以确定哪些选定的时钟信号产生有效的RX模式信号。然后，RX电路能够选择一个相移时钟信号，以用于从TX电路接收的RX数据信号的正常处理。

30. 发明申请

US20110060433A1 BILINEAR ALGORITHMS AND VLSI IMPLEMENTATIONS OF FORWARD AND INVERSE MDCT WITH APPLICATIONS TO MP3 AUDIO 审中-公开
标题翻译：前向和反向MDCT的双向算法和VLSI实现应用于MP3音频
公开(公告)号：US20110060433A1
公开(公告)日：2011-03-10
申请号：US12865831
申请日：2009-02-02
申请人： Xingdong Dai , Meghanad Wagh
发明人： Xingdong Dai , Meghanad Wagh
IPC分类号： G06F17/00
CPC分类号： G06F17/147 , G10L19/0212 , G10L19/16
摘要： Provided herein are hardware efficient bilinear algorithms and methods to compute MDCT/IMDCT of 2̂n and 4.3̂n points. The algorithms and methods for composite lengths have practical applications in MP3 audio encoding and decoding. The MDT/IMDCT can be converted to type-IV discrete cosine transforms (DCT-IV). Using group theory, the methods decomposes DCT-IV transform kernel matrix into groups of cyclic and Hankel product matrices. Bilinear algorithms are then applied to efficiently evaluate these groups. When implemented in VLSI, bilinear algorithms have improved the critical path delays over existing solutions. For MPEG-1/2 layer III (MP3) audio, proposed herein are several different versions of unified hardware architectures for both the short and long blocks and the forward and inverse transforms.
摘要翻译：本文提供了硬件有效的双线性算法和方法来计算2n和4.3n点的MDCT / IMDCT。复合长度的算法和方法在MP3音频编码和解码中具有实际应用。 MDT / IMDCT可以转换为IV型离散余弦变换（DCT-IV）。利用群体理论，将DCT-IV变换核心矩阵分解为循环和汉克尔乘积矩阵。然后应用双线性算法来有效地评估这些组。当在VLSI中实现时，双线性算法已经改进了现有解决方案的关键路径延迟。对于MPEG-1/2 Layer III（MP3）音频，本文提出了用于短块和长块以及正向和反向变换的统一硬件架构的几种不同版本。

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