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21. 发明授权

US5377231A Automatic gain control circuit for a digital baseband line equalizer 失效
标题翻译：用于数字基带线均衡器的自动增益控制电路
公开(公告)号：US5377231A
公开(公告)日：1994-12-27
申请号：US159402
申请日：1993-11-30
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H03G3/20 , H04B3/04 , H04B3/06 , H04M3/40 , H04L27/08
CPC分类号： H04M3/40 , H04B3/04
摘要： An automatic gain control circuit produces a control voltage for a digital baseband line equalizer having a ternary output signal. The circuit includes a capacitor for storing a charge to produce the control voltage, a charge circuit for charging the capacitor if the amplitude of the ternary output signal exceeds a reference voltage, and a discharging circuit for discharging the capacitor only when the ternary output signal is at a non-zero level.
摘要翻译：自动增益控制电路产生具有三进制输出信号的数字基带线均衡器的控制电压。电路包括用于存储产生控制电压的电荷的电容器，如果三元输出信号的幅度超过参考电压，则对电容器充电的充电电路，以及仅当三元输出信号为处于非零级。

22. 发明授权

US07777585B1 Passive temperature compensation for an oscillator 有权
标题翻译：振荡器的被动温度补偿
公开(公告)号：US07777585B1
公开(公告)日：2010-08-17
申请号：US12145647
申请日：2008-06-25
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H03L1/02
CPC分类号： H03L1/02 , H03B5/1206
摘要： A technique for reducing temperature sensitivity of an LC oscillator circuit includes a passive circuit coupled in parallel with a load capacitor. In at least one embodiment, an oscillator circuit is configured to generate a periodic signal having a free-running frequency. The oscillator circuit includes a first circuit portion including at least one inductor coupled in parallel with at least one load capacitor. The first circuit portion has an inductance-capacitance product that has a first temperature sensitivity. The oscillator circuit includes a passive circuit portion coupled in parallel with the first circuit portion. The passive circuit portion includes at least one resistor in series with at least one capacitor. The passive circuit portion has a second temperature sensitivity that opposes an effect of the first temperature sensitivity on the free-running frequency of the oscillator circuit, thereby reducing temperature sensitivity of the free-running frequency.
摘要翻译：用于降低LC振荡器电路的温度灵敏度的技术包括与负载电容并联耦合的无源电路。在至少一个实施例中，振荡器电路被配置为产生具有自由运行频率的周期信号。振荡器电路包括第一电路部分，其包括与至少一个负载电容器并联耦合的至少一个电感器。第一电路部分具有具有第一温度灵敏度的电感电容产品。振荡器电路包括与第一电路部分并联耦合的无源电路部分。无源电路部分包括与至少一个电容器串联的至少一个电阻器。无源电路部分具有与第一温度灵敏度对振荡器电路的自由运行频率的影响相反的第二温度灵敏度，从而降低自由运行频率的温度灵敏度。

23. 发明授权

US07742352B1 Variable sense level for fuse-based non-volatile memory 有权
标题翻译：基于熔丝的非易失性存储器的可变感应电平
公开(公告)号：US07742352B1
公开(公告)日：2010-06-22
申请号：US11927845
申请日：2007-10-30
申请人： Susumu Hara , Jeffrey S. Batchelor , Jeffrey L. Sonntag
发明人： Susumu Hara , Jeffrey S. Batchelor , Jeffrey L. Sonntag
IPC分类号： G11C7/02
CPC分类号： G11C17/18 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/027 , G11C29/12005 , G11C29/48 , G11C29/50008
摘要： Techniques for use with a fuse-based non-volatile memory circuit include digitally controlling a resistance threshold of the circuit. The circuit includes a fuse circuit and a comparator circuit. The comparator circuit is configured to compare a first signal indicative of the fuse resistance to a second signal indicative of a reference level. At least one of the first and second signals is digitally controllable. The comparator circuit is configured to generate a digital output signal indicative of the comparison. The circuit may include a first digital-to-analog converter circuit configured to generate a first analog signal based on at least a first plurality of digital signals. The first signal is at least partially based on the first analog signal. The circuit may include a control circuit configured to digitally control the digitally controllable ones of the first and second signals at least partially based on the digital output signal.
摘要翻译：与基于熔丝的非易失性存储器电路一起使用的技术包括数字地控制电路的电阻阈值。电路包括熔丝电路和比较器电路。比较器电路被配置为将指示熔丝电阻的第一信号与指示参考电平的第二信号进行比较。第一和第二信号中的至少一个是数字可控的。比较器电路被配置为产生指示比较的数字输出信号。电路可以包括被配置为基于至少第一多个数字信号产生第一模拟信号的第一数模转换器电路。第一信号至少部分地基于第一模拟信号。电路可以包括控制电路，其被配置为至少部分地基于数字输出信号数字地控制第一和第二信号中的数字可控的信号。

24. 发明授权

US06249398B1 Class of fixed partial response targets in a PRML sampled data detection channel 失效
标题翻译： PRML采样数据检测通道中固定部分响应目标的类别
公开(公告)号：US06249398B1
公开(公告)日：2001-06-19
申请号：US09034933
申请日：1998-03-04
申请人： Kevin Fisher , Kelly K. Fitzpatrick , Cory Modlin , Ara Patapoutian , Jeffrey L. Sonntag , Necip Sayiner
发明人： Kevin Fisher , Kelly K. Fitzpatrick , Cory Modlin , Ara Patapoutian , Jeffrey L. Sonntag , Necip Sayiner
IPC分类号： G11B5035
CPC分类号： G11B20/10055 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10296
摘要： A new class of fixed partial response targets are disclosed for use in a PRML magnetic medium read channel. The preferred embodiment exhibits an equalization response characterized by the polynomial 7+4*D−4*D2−5*D3−2*D4, where D represents the unit delay operator. This read channel target provides improved matching to the inherent magnetic channel over the known canonical class of targets (1−D)(1+D){circumflex over ( )}N, and thereby reduces equalization losses. The improved spectral matching reduces amplification of noise in the channel, thereby reducing bit-error-rates. The new class of targets also exhibits a spectral null at DC, reducing problems for offset cancellation circuitry and making the disk drive less sensitive to thermal asperities. It also exhibits a spectral depression rather than a spectral null at the Nyquist frequency, making quasi-catastrophic error sequences virtually impossible. The new class of target simplifies coding and allows RLL code ratios that approach unity, improving effective recording densities, while significantly reducing BER.
摘要翻译：公开了一类新的固定部分响应目标，用于PRML磁介质读取通道。优选实施例表现出由多项式7 + 4 * D-4 * D2-5 * D3-2 * D4表征的均衡响应，其中D表示单位延迟算子。这个读通道目标在已知的典型目标类别（1-D）（1 + D）{circumflex over（）} N上提供与固有磁通道的改进的匹配，从而减少均衡损失。改进的频谱匹配减少了信道中噪声的放大，从而降低了误码率。新类别的目标还在DC处表现出光谱零点，减少偏移消除电路的问题，并使磁盘驱动器对热凹凸不敏感。在奈奎斯特频率下，它也表现出光谱抑制而不是光谱零点，使得准灾难性误差序列实际上是不可能的。新类别的目标简化了编码，并允许RLL代码比率达到统一，提高了有效的记录密度，同时显着降低了BER。

25. 发明授权

US5550528A Matching of digital patterns using analog logic 失效
标题翻译：使用模拟逻辑匹配数字模式
公开(公告)号：US5550528A
公开(公告)日：1996-08-27
申请号：US397700
申请日：1995-03-01
申请人： Glen E. Offord , Jeffrey L. Sonntag
发明人： Glen E. Offord , Jeffrey L. Sonntag
IPC分类号： G06G7/14 , G06F7/02 , H03K19/20 , G05B1/00
CPC分类号： G06F7/02
摘要： A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.
摘要翻译：匹配数字模式的快速，低功耗和小尺寸方法提供了逐位比较与参考模式的比较，以确定匹配。在说明性实施例中，每个不匹配打开电流源。当不匹配的电流超过最大电流吸收值时，模式失配输出变高。参考模式以及必须匹配的位数可以方便地进行可编程。这种方法在“模糊”匹配中特别有用，其中M位模式的任何N位必须匹配以考虑匹配的模式。

26. 发明授权

US09921683B2 Detection of defects in touch sensors 有权
公开(公告)号：US09921683B2
公开(公告)日：2018-03-20
申请号：US13483465
申请日：2012-05-30
申请人： Daniel J. Cooley , Jeffrey L. Sonntag
发明人： Daniel J. Cooley , Jeffrey L. Sonntag
IPC分类号： G01R31/02 , G06F3/045 , G06F3/041
CPC分类号： G06F3/0418 , G01R31/025
摘要： Defects in a touch sensor are detected by coupling the sensor lines to a common signal line. Each of the sensor lines is tested by disconnecting the sensor line from the common signal line, connecting it to a voltage (e.g., ground) and comparing the voltage on the common signal line to a reference voltage. Detected defects include a short circuit between any two transmit and/or receive lines and a short between any transmit or receive line to ground.

27. 发明授权

US09584133B2 Temperature compensated oscillator with improved noise performance 有权
标题翻译：具有改善噪声性能的温度补偿振荡器
公开(公告)号：US09584133B2
公开(公告)日：2017-02-28
申请号：US13485356
申请日：2012-05-31
申请人： Volodymyr Kratyuk , Jeffrey L. Sonntag , Aaron J. Caffee
发明人： Volodymyr Kratyuk , Jeffrey L. Sonntag , Aaron J. Caffee
IPC分类号： G05F1/577 , H03L1/02 , G05F3/24 , H03L7/00 , H02M3/07 , H01L23/50 , H03K3/011 , H03K3/03
CPC分类号： H03L1/022 , G05F3/242 , H01L23/50 , H01L2924/0002 , H02M3/07 , H03K3/011 , H03K3/03 , H03L7/00 , H01L2924/00
摘要： An oscillator system addresses power supply noise and temperature dependence. The system includes a multi-stage regulator circuit that receives a supply voltage and generates a lower voltage oscillator supply voltage that is less noisy than the supply voltage. A charge pump circuit receives the oscillator supply voltage and the oscillator output signal and supplies the regulator circuit with a boosted voltage. A reference generator circuit supplies a reference signal that is used to determine the oscillator supply voltage. The reference signal varies with temperature and is used to offset the temperature coefficient of the oscillator.
摘要翻译：振荡器系统解决电源噪声和温度依赖性。该系统包括多级调节器电路，其接收电源电压并产生比电源电压噪声较小的较低电压振荡器电源电压。电荷泵电路接收振荡器电源电压和振荡器输出信号，并向稳压器电路提供升压电压。参考发生器电路提供用于确定振荡器电源电压的参考信号。参考信号随温度变化，用于抵消振荡器的温度系数。

28. 发明授权

US08934528B2 Transition interval coding for serial communication 有权
标题翻译：串行通信的转换间隔编码
公开(公告)号：US08934528B2
公开(公告)日：2015-01-13
申请号：US13076155
申请日：2011-03-30
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H03K7/04 , H04L25/49 , H04L25/06
CPC分类号： H04L25/4902 , H04L25/061
摘要： A one-wire transmission protocol utilizes transition interval coding in which a value of a transmitted symbol is determined by comparing an interval length between the voltage transition associated with the transmitted symbol and a prior voltage transition on the communication link, to a threshold transition interval provided to the receiving device during the transmission sequence that includes the transmitted symbol. If the interval length of the symbol is below the transition interval threshold, the symbol is determined to be a first value and if the interval length of the symbol is above the transition interval threshold, the symbol is determined to be a second value. The transition interval threshold is provided in a start sequence that includes at least two transitions. The threshold transition interval width is based on one or more transition intervals determined during the start sequence.
摘要翻译：一线传输协议使用转换间隔编码，其中通过将与发送符号相关联的电压转换与通信链路上的先前电压转换之间的间隔长度与所提供的阈值转换间隔进行比较来确定发送符号的值在包括发送符号的发送序列期间到接收设备。如果符号的间隔长度低于转换间隔阈值，则将符号确定为第一值，并且如果符号的间隔长度高于转换间隔阈值，则将该符号确定为第二值。过渡间隔阈值以包括至少两个转变的起始序列提供。阈值转换间隔宽度基于在开始序列期间确定的一个或多个过渡间隔。

29. 发明授权

US6043715A Phase-locked loop with static phase offset compensation 有权
标题翻译：具有静态相位补偿的锁相环
公开(公告)号：US6043715A
公开(公告)日：2000-03-28
申请号：US144916
申请日：1998-09-01
申请人： James A. Bailey , Angelo R. Mastrocola , Jeffrey L. Sonntag , William B. Wilson
发明人： James A. Bailey , Angelo R. Mastrocola , Jeffrey L. Sonntag , William B. Wilson
IPC分类号： H03L7/087 , H03L7/089 , G09F13/26
CPC分类号： H03L7/0898 , H03L7/087
摘要： A phase-locked loop (PLL) has a master circuit configured to a slave circuit. The slave circuit has a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator configured to operate as a closed-loop PLL. The master circuit has a phase detector and a charge pump that are similar to the corresponding components in the slave circuit. The master circuit is configured to receive two input signals with zero phase offset. As such, any net current charge generated by the master charge pump will be indicative of mismatch within the master phase detector and charge pump, and therefore, by analogy, indicative of mismatch within the slave phase detector and charge pump, as well. A voltage signal generated by the master circuit is applied to control the generation of currents by the slave charge pump in such a way as to compensate for static phase offset that would otherwise exist in the slave circuit.
摘要翻译：锁相环（PLL）具有配置成从电路的主电路。从电路具有相位检测器，电荷泵，环路滤波器和被配置为作为闭环PLL工作的压控振荡器。主电路具有与从电路中的相应部件相似的相位检测器和电荷泵。主电路被配置为接收具有零相位偏移的两个输入信号。因此，由主电荷泵产生的任何净电流电荷将指示主相位检测器和电荷泵内的失配，并且因此类似地指示从相检测器和电荷泵内的失配。由主电路产生的电压信号被施加以控制从电荷泵的电流产生，以补偿否则存在于从电路中的静态相位偏移。

30. 发明授权

US4818929A Fully differential analog comparator 失效
标题翻译：全差分模拟比较器
公开(公告)号：US4818929A
公开(公告)日：1989-04-04
申请号：US214561
申请日：1988-07-01
申请人： Jeffrey L. Sonntag , Thayamkulangara R. Viswanathan , William B. Wilson
发明人： Jeffrey L. Sonntag , Thayamkulangara R. Viswanathan , William B. Wilson
IPC分类号： G01R19/165 , H03F3/45 , H03K5/08 , H03M1/34 , G05F3/24
CPC分类号： H03F3/45237 , H03F3/4565 , H03F2203/45711
摘要： A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.

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