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21. 发明授权

US6131134A Hot plug-and-play converter of a universal serial bus interface 失效
标题翻译：通用串行总线接口的热插拔式转换器
公开(公告)号：US6131134A
公开(公告)日：2000-10-10
申请号：US123569
申请日：1998-07-27
申请人： Yi-Chen Huang , Ming-Shang Chen
发明人： Yi-Chen Huang , Ming-Shang Chen
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： A hot plug-and-play (PnP) converter of a universal serial bus (USB) interface that converts a non-PnP interface into a hot PnP USB interface. The converter sends the information related to the converter itself to the connected computer system, and sends the information related to the connected peripheral as well as to the presence of the peripheral to the computer system. Users can handle the connection status of disclosed is a connected peripheral more directly. The converter further instructs the computer system to detect the connection status of a peripheral automatically by changing the connection of the pull-up resistor of the transferring wire on the USB interface.
摘要翻译：通用串行总线（USB）接口的热插拔（PnP）转换器，将非PnP接口转换为热PnP USB接口。转换器将与转换器本身相关的信息发送到连接的计算机系统，并将与连接的外设相关的信息以及外设的存在发送到计算机系统。用户可以更直接地处理连接外设的连接状态。转换器进一步指示计算机系统通过改变USB接口上传输线的上拉电阻的连接来自动检测外设的连接状态。

22. 发明授权

US07776690B2 Method of forming a contact on a semiconductor device 有权
标题翻译：在半导体器件上形成接触的方法
公开(公告)号：US07776690B2
公开(公告)日：2010-08-17
申请号：US11691501
申请日：2007-03-27
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.
摘要翻译：提供了一种在半导体器件上形成接触的方法。首先，提供基板。由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。位于字线下方并由扩散区隔离的栅极结构。然后，形成蚀刻停止层。蚀刻停止层和第一介电层具有不同的蚀刻选择性。第二介质层形成在衬底上。此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

23. 发明申请

US20080138998A1 METHODS FOR MANUFACTURING MEMORY AND LOGIC DEVICES USING THE SAME PROCESS WITHOUT THE NEED FOR ADDITIONAL MASKS 有权
标题翻译：使用相同工艺制造存储器和逻辑器件的方法，而不需要额外的掩码
公开(公告)号：US20080138998A1
公开(公告)日：2008-06-12
申请号：US11609747
申请日：2006-12-12
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/3144 , H01L21/02238 , H01L21/02255 , H01L21/28238 , H01L21/31662 , H01L29/42332 , H01L29/518 , H01L29/66825 , H01L29/78 , H01L29/7883 , H01L29/7885
摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.
摘要翻译：半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。然而，额外的步骤不需要额外的掩模。因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

24. 发明申请

US20070190719A1 METHOD OF FORMING A CONTACT ON A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件上形成接触的方法
公开(公告)号：US20070190719A1
公开(公告)日：2007-08-16
申请号：US11691501
申请日：2007-03-27
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L21/8242
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.
摘要翻译：提供了一种在半导体器件上形成接触的方法。首先，提供基板。由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。位于字线下方并由扩散区隔离的栅极结构。然后，形成蚀刻停止层。蚀刻停止层和第一介电层具有不同的蚀刻选择性。第二介质层形成在衬底上。此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

25. 发明授权

US07214983B2 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07214983B2
公开(公告)日：2007-05-08
申请号：US10904703
申请日：2004-11-24
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.
摘要翻译：提供了一种制造非易失性存储器的方法。在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板上形成多个源极/漏极区域。在源/漏区上形成多个介质条。多个字线形成在堆叠栅极条和介质条上。此后，除去由字线露出的堆叠栅极条以形成多个开口。在开口和字线的侧壁上形成多个间隔物。介电层形成在衬底上。在电介质层和两个相邻字线之间的介质条形成多个触点。

26. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

27. 发明申请

US20090011594A1 Methods of Trench and Contact Formation in Memory Cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US20090011594A1
公开(公告)日：2009-01-08
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

28. 发明授权

US07399674B2 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US07399674B2
公开(公告)日：2008-07-15
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

29. 发明申请

US20060086968A1 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US20060086968A1
公开(公告)日：2006-04-27
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

30. 发明授权

US08593850B2 Diode-less array for one-time programmable memory 有权
公开(公告)号：US08593850B2
公开(公告)日：2013-11-26
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , G11C17/06 , G11C17/18
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

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