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21. 发明申请

US20130158342A1 PHOTOCHEMICAL TISSUE BONDING 审中-公开
标题翻译：化学组织结合
公开(公告)号：US20130158342A1
公开(公告)日：2013-06-20
申请号：US13543137
申请日：2012-07-06
申请人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
发明人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
IPC分类号： A61B17/11
CPC分类号： A61B17/11 , A61B2017/00508 , A61B2017/00517 , A61F9/0079 , A61F9/0081 , A61F9/00821 , A61F2009/00842 , A61F2009/00853 , A61F2009/00872 , A61F2009/00887 , A61L24/001 , A61L2430/32 , A61N5/062
摘要： Photochemical tissue boding methods for bonding neural tissues include the application of a photosensitizer to a tissue and/or tissue graft, followed by irradiation with electromagnetic energy to produce a tissue seal. The methods are useful for tissue adhesion, such as in wound closure, tissue grafting, skin grafting, musculoskeletal tissue repair, ligament or tendon repair, neural repair, blood vessel repair and corneal repair.
摘要翻译：用于粘合神经组织的光化学组织编织方法包括将光敏剂施用于组织和/或组织移植物，随后用电磁能照射以产生组织密封。该方法可用于组织粘连，例如伤口闭合，组织移植，皮肤移植，肌肉骨骼组织修复，韧带或肌腱修复，神经修复，血管修复和角膜修复。

22. 发明授权

US07206224B1 Methods and systems for high write performance in multi-bit flash memory devices 有权
公开(公告)号：US07206224B1
公开(公告)日：2007-04-17
申请号：US11037477
申请日：2005-01-18
申请人： Mark Randolph , Darlene Hamilton , Roni Kornitz
发明人： Mark Randolph , Darlene Hamilton , Roni Kornitz
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C2211/5641
摘要： Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

23. 发明申请

US20060291282A1 Flash memory cell and methods for programming and erasing 有权
公开(公告)号：US20060291282A1
公开(公告)日：2006-12-28
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

24. 发明申请

US20060268593A1 Read-only memory array with dielectric breakdown programmability 审中-公开
标题翻译：具有介电击穿可编程性的只读存储阵列
公开(公告)号：US20060268593A1
公开(公告)日：2006-11-30
申请号：US11136981
申请日：2005-05-25
申请人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
发明人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C2213/72 , H01L27/1021 , H01L27/112 , H01L27/11206 , H01L27/118
摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.
摘要翻译：根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。可编程ROM阵列还包括位于至少一个位线上的至少一个字线。可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。编程操作使存储单元作为二极管工作。可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

25. 发明授权

US07120063B1 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07120063B1
公开(公告)日：2006-10-10
申请号：US10841850
申请日：2004-05-07
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

26. 发明授权

US06999918B2 Method and apparatus to facilitate correlating symbols to sounds 有权
标题翻译：便于将符号与声音相关联的方法和装置
公开(公告)号：US06999918B2
公开(公告)日：2006-02-14
申请号：US10251354
申请日：2002-09-20
申请人： Changxue Ma , Mark Randolph
发明人： Changxue Ma , Mark Randolph
IPC分类号： G10L13/00 , G06F17/21
CPC分类号： G10L13/08
摘要： A dictionary is comprised of a dendroid hierarchy of branches and nodes, wherein each node represents no more than one symbol (which symbol is to be converted to a corresponding sound) and wherein each such symbol as is represented at a given node has only one corresponding sound associated with that symbol at that node. In addition, many of the branches include a plurality of nodes representing a string of the symbols in a particular sequence. The dictionary is used to translate an input comprising a given integral sequence of the symbols into a corresponding integral sequence of sounds. This permits both method and apparatus to convert, for example, text to representative phonemes. Such phonemes can be used, amongst other purposes, to support synthesized speech production.
摘要翻译：字典由分支和节点的树状分层组成，其中每个节点表示不超过一个符号（该符号将被转换为对应的声音），并且其中在给定节点处表示的每个这样的符号只有一个对应在该节点处与该符号相关联的声音。此外，许多分支包括表示特定序列中的符号串的多个节点。字典用于将包括符号的给定整数序列的输入转换成相应的整体声音序列。这允许方法和装置将例如文本转换为代表性音素。除了其它目的之外，还可以使用这样的音素来支持合成语音制作。

27. 发明申请

US20050153508A1 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
公开(公告)号：US20050153508A1
公开(公告)日：2005-07-14
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
发明人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

28. 发明授权

US07630253B2 Flash memory programming and verification with reduced leakage current 有权
标题翻译：闪存编程和验证，减少漏电流
公开(公告)号：US07630253B2
公开(公告)日：2009-12-08
申请号：US11398415
申请日：2006-04-05
申请人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
发明人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译：根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

29. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

30. 发明授权

US07339222B1 Method for determining wordline critical dimension in a memory array and related structure 有权
标题翻译：用于确定存储器阵列和相关结构中的字线临界尺寸的方法
公开(公告)号：US07339222B1
公开(公告)日：2008-03-04
申请号：US11416551
申请日：2006-05-03
申请人： Meng Ding , Hidehiko Shiraiwa , Mark Randolph
发明人： Meng Ding , Hidehiko Shiraiwa , Mark Randolph
IPC分类号： H01L27/108
CPC分类号： H01L27/115 , H01L27/11517 , Y10S257/905
摘要： According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.
摘要翻译：根据一个示例性实施例，一种用于制造存储器阵列的方法包括在衬底中形成多个沟槽，其中沟槽确定衬底中的多个字线区域，其中每个字线区域位于两个相邻的沟槽之间，以及其中每个字线区域具有字线区域宽度。存储器阵列可以是闪存阵列。该方法还包括在衬底中形成多个位线，其中位线垂直于沟槽定位。该方法还包括在每个沟槽中形成电介质区域。该方法还包括在位线，字线区域和沟槽之间形成电介质叠层。该方法还包括形成多个字线，其中每个字线位于一个字线区域上。字线区域宽度决定每个字线的有效字线宽度。

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