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21. 发明授权

US08862426B2 Method and test system for fast determination of parameter variation statistics 有权
标题翻译：方法和测试系统，用于快速确定参数变化统计
公开(公告)号：US08862426B2
公开(公告)日：2014-10-14
申请号：US11961442
申请日：2007-12-20
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R19/00 , G01R31/00 , G01R31/14 , G01R31/28 , G01R31/3185
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译：用于快速确定参数变化统计的方法和测试系统提供了使用低计算能力和容易获得的测试设备来确定过程变化和参数统计的机制。在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。阵列的测试输出提供依赖于特定器件参数的电流或电压。器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

22. 发明授权

US08458620B2 Gradient-based search mechanism for optimizing photolithograph masks 失效
公开(公告)号：US08458620B2
公开(公告)日：2013-06-04
申请号：US13531831
申请日：2012-06-25
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

23. 发明授权

US08453074B2 Gradient based search mechanism for optimizing photolithograph masks 失效
标题翻译：基于梯度的搜索机制，用于优化光刻胶掩模
公开(公告)号：US08453074B2
公开(公告)日：2013-05-28
申请号：US13531733
申请日：2012-06-25
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.
摘要翻译：提供了一种用于优化光刻胶掩模的机构。收到给定的目标模式。从给定的目标图案生成初始的虚构掩模，并且选择alpha2的初始值，其中使用α2的初始值来确定光强度和晶片图像。然后确定初始虚拟掩模中的每个像素的光强度和初始虚构掩模中每个像素的晶片图像。然后通过将从虚构掩模生成的晶片图像与给定的目标图案进行比较来确定是否已经实现了会聚。响应于从虚构掩模生成的晶片图像到给定目标图案的会聚，产生用于将图像转印到晶片的最终掩模。

24. 发明申请

US20130061185A1 MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY 有权
标题翻译：多功能拼图的掩蔽分配
公开(公告)号：US20130061185A1
公开(公告)日：2013-03-07
申请号：US13223706
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70466 , G03F7/70475
摘要： A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.
摘要翻译：提供了用于三重图案化光刻的掩模分配的机构。该机制通过设计规则相关的投影来识别尖端到尖端（TT），尖端到侧面（TS）以及侧向（SS）冲突部分。该机制分别查找TT，TS和SS冲突的针脚位置。机制颜色TT，TS和SS冲突部分与mask0 / mask1，mask0 / mask2，mask1 / mask2着色循环，每种类型分别着色。该机制使用现有的双向着色基础设施。作为第一个目标，该机制试图尽量减少冲突。作为第二个目的，该机构通过将针脚的两侧分配到相同的面罩来尝试最小化线迹数。一旦完成所有冲突部分的着色，该机制将颜色非冲突部分，以最大化曝光的最小重叠，并且如果双面是不同的颜色，则使用两种颜色，如果两面是相同颜色，则使用一种颜色。

25. 发明授权

US08347240B2 Split-layer design for double patterning lithography 有权
标题翻译：双层图案平版印刷的分层设计
公开(公告)号：US08347240B2
公开(公告)日：2013-01-01
申请号：US12915923
申请日：2010-10-29
申请人： Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G03F1/70 , H01L27/0207
摘要： A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.
摘要翻译：提供了一种用于将一组单层设计规则转换为用于双重图案化光刻（DPL）的一组分裂层设计规则的机制。确定了一套单层设计规则和单次曝光的最小光刻分辨率间距约束。单层设计规则的集合包括单层设计中的一组第一形状所需的第一多个最小距离。关于单次曝光的最小光刻分辨率间距约束修改单层设计规则集合中的第一多个最小距离中的每一个，从而形成分裂层设计规则集合。分裂层设计规则的集合包括一组第二形状所需的第二多个最小距离和分裂层设计中的一组第三形状。然后将该组分裂设计规则编码为设计规则检查器。

26. 发明申请

US20120262187A1 TEST CIRCUIT FOR BIAS TEMPERATURE INSTABILITY RECOVERY MEASUREMENTS 失效
标题翻译：用于偏温不稳定性恢复测量的测试电路
公开(公告)号：US20120262187A1
公开(公告)日：2012-10-18
申请号：US13524208
申请日：2012-06-15
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01R27/28
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法和测试电路提供测量，以准确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

27. 发明申请

US20120260221A1 Gradient-Based Search Mechanism for Optimizing Photolithograph Masks 失效
公开(公告)号：US20120260221A1
公开(公告)日：2012-10-11
申请号：US13531754
申请日：2012-06-25
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

28. 发明授权

US08214777B2 On-chip leakage current modeling and measurement circuit 有权
标题翻译：片内漏电流建模与测量电路
公开(公告)号：US08214777B2
公开(公告)日：2012-07-03
申请号：US12419377
申请日：2009-04-07
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

29. 发明授权

US08151230B2 Blended model interpolation 有权
标题翻译：混合模型插值
公开(公告)号：US08151230B2
公开(公告)日：2012-04-03
申请号：US12420879
申请日：2009-04-09
申请人： Emrah Acar , Damir Jamsek , Sani R. Nassif
发明人： Emrah Acar , Damir Jamsek , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/318357
摘要： According to the illustrative embodiments, a data structure is accessed to determine a set of known data points surrounding a queried data point having an input value and an output value, the set of known data points including first, second and third data points. First and second curves are built from the first, second and third data points utilizing a first approximate model and a second approximate model. A weighting parameter value is determined by which the first curve and second curve are blended at the second data point. The output value of the queried data point is determined and stored by blending the first curve and the second curve utilizing the input value of the queried data point and the weighting parameter value.
摘要翻译：根据说明性实施例，访问数据结构以确定围绕具有输入值和输出值的查询数据点的一组已知数据点，该组已知数据点包括第一，第二和第三数据点。使用第一近似模型和第二近似模型，从第一，第二和第三数据点构建第一和第二曲线。通过第一曲线和第二曲线在第二数据点处混合加权参数值。使用查询数据点的输入值和加权参数值，通过混合第一曲线和第二曲线来确定和存储查询数据点的输出值。

30. 发明申请

US20110035709A1 Gradient-Based Search Mechanism for Optimizing Photolithograph Masks 有权
标题翻译：基于梯度的搜索机制优化光刻胶掩模
公开(公告)号：US20110035709A1
公开(公告)日：2011-02-10
申请号：US12536090
申请日：2009-08-05
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.
摘要翻译：提供了一种用于优化光刻胶掩模的机构。收到给定的目标模式。从给定的目标图案生成初始虚拟掩模，并且选择初始值α2，其中使用初始值α2来确定光强度和晶片图像。然后确定初始虚拟掩模中的每个像素的光强度和初始虚构掩模中每个像素的晶片图像。然后通过将从虚构掩模生成的晶片图像与给定的目标图案进行比较来确定是否已经实现了会聚。响应于从虚构掩模生成的晶片图像到给定目标图案的会聚，产生用于将图像转印到晶片的最终掩模。

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