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21. 发明申请

US20070105375A1 Catalytic nucleation monolayer for metal seed layers 有权
标题翻译：催化成核单层金属种子层
公开(公告)号：US20070105375A1
公开(公告)日：2007-05-10
申请号：US11269402
申请日：2005-11-07
申请人： Adrien Lavoie , Arnel Fajardo , Valery Dubin
发明人： Adrien Lavoie , Arnel Fajardo , Valery Dubin
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76873 , H01L21/76876
摘要： A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.
摘要翻译：在衬底上形成铜互连的方法包括提供衬底，该衬底包括介电层和蚀刻到电介质层中的沟槽，使用钯固定法在阻挡层中沉积势垒层，以在阻挡层上形成金属催化剂层层，激活金属催化剂层，并使用气相沉积工艺将铜籽晶层沉积到金属催化剂层上。气相沉积工艺可以包括PVD，CVD或ALD。然后可以使用电镀工艺或无电电镀工艺将块状铜层沉积到铜种子层上以填充沟槽。可以进行平面化处理以形成最终的互连结构。

22. 发明申请

US20060281306A1 Carbon nanotube interconnect contacts 审中-公开
标题翻译：碳纳米管互连触点
公开(公告)号：US20060281306A1
公开(公告)日：2006-12-14
申请号：US11148614
申请日：2005-06-08
申请人： Florian Gstrein , Adrien Lavoie , Valery Dubin , Juan Dominguez
发明人： Florian Gstrein , Adrien Lavoie , Valery Dubin , Juan Dominguez
IPC分类号： H01L21/44
CPC分类号： H01L23/53276 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect on a semiconductor substrate comprises providing at least one carbon nanotube within a trench, etching at least one portion of the carbon nanotube to create an opening, conformally depositing a metal layer on the carbon nanotube through the opening, and forming a metallized contact at the opening that is substantially coupled to the carbon nanotube. The metal layer may be conformally deposited on the carbon nanotube using an atomic layer deposition process or an electroless plating process. Multiple metal layers may be deposited to substantially fill voids within the carbon nanotube. The electroless plating process may use a supercritical liquid as the medium for the plating solution. The wetting behavior of the carbon nanotube may be modified prior to the electroless plating process to increase the hydrophilicity of the carbon nanotube.
摘要翻译：一种用于在半导体衬底上形成互连的方法包括在沟槽内提供至少一个碳纳米管，蚀刻碳纳米管的至少一部分以形成开口，通过开口在碳纳米管上共形沉积金属层，并形成在开口处的金属化接触基本上与碳纳米管耦合。可以使用原子层沉积工艺或无电镀工艺将金属层共形沉积在碳纳米管上。可以沉积多个金属层以基本上填充碳纳米管内的空隙。化学镀处理可以使用超临界液体作为电镀溶液的介质。可以在化学镀处理之前改变碳纳米管的润湿性能，以增加碳纳米管的亲水性。

23. 发明申请

US20060044759A1 Electroosmotic pump apparatus that generates low amount of hydrogen gas 有权
标题翻译：产生少量氢气的电渗泵设备
公开(公告)号：US20060044759A1
公开(公告)日：2006-03-02
申请号：US10928861
申请日：2004-08-26
申请人： Ramanan Chebiam , Valery Dubin
发明人： Ramanan Chebiam , Valery Dubin
IPC分类号： H05K7/20
CPC分类号： F04B19/006 , H01L23/473 , H01L2924/0002 , H01L2924/00
摘要： An apparatus that includes an electroosmotic pump and an aqueous or nonaqueous electrolyte liquid and generates relatively low amount of hydrogen gas is described herein. The apparatus may further include a hydrogen absorber.
摘要翻译：本文描述了一种包括电渗泵和水或非水电解液并产生相对低量的氢气的装置。该装置还可以包括氢吸收剂。

24. 发明授权

US06933230B2 Method for making interconnects and diffusion barriers in integrated circuits 失效
标题翻译：在集成电路中制作互连和扩散屏障的方法
公开(公告)号：US06933230B2
公开(公告)日：2005-08-23
申请号：US10093898
申请日：2002-03-08
申请人： Valery Dubin
发明人： Valery Dubin
IPC分类号： H01L21/288 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/288 , H01L21/76807 , H01L21/7682 , H01L21/76879 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.
摘要翻译：发明人设计了形成互连的方法，其导致导电结构具有较少的空隙并因此降低了电阻。该方法的一个实施例从具有孔和沟槽的绝缘层开始，使用选择性无电沉积填充孔，并使用覆盖沉积填充沟槽。该方法的另一个实施方案在无电沉积之前在金属上添加抗结合材料，例如表面活性剂，并且在沉积之后除去至少一些表面活性剂，以在孔的沉积的金属和内侧壁之间形成间隙，并且沟渠该间隙用作扩散屏障。另一个实施方案将表面活性剂留在适当位置以用作扩散阻挡层。这些和其它实施例最终促进集成电路的速度，效率或制造。

25. 发明申请

US20050167755A1 Microcircuit fabrication and interconnection 有权
公开(公告)号：US20050167755A1
公开(公告)日：2005-08-04
申请号：US11048231
申请日：2005-02-01
申请人： Valery Dubin , Mark Bohr
发明人： Valery Dubin , Mark Bohr
IPC分类号： H01J1/02 , H01L21/3205 , H01L21/335 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/76 , B82Y10/00 , H01L21/768 , H01L21/76879 , H01L21/76897 , H01L23/485 , H01L23/53276 , H01L29/66439 , H01L29/7613 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

26. 发明申请

US20050147762A1 Method to fabricate amorphous electroless metal layers 审中-公开
标题翻译：制造无定形无电金属层的方法
公开(公告)号：US20050147762A1
公开(公告)日：2005-07-07
申请号：US10749776
申请日：2003-12-30
申请人： Valery Dubin , Chin-Chang Cheng , Chih-I Wu
发明人： Valery Dubin , Chin-Chang Cheng , Chih-I Wu
IPC分类号： B05D1/18 , B32B3/00 , C23C18/16 , C23C18/31 , C23C18/32 , C23C18/34 , H01L21/288 , H01L21/768 , H01L23/532 , H05H1/24
CPC分类号： H01L21/76849 , C23C18/1607 , C23C18/1689 , C23C18/1831 , C23C18/31 , C23C18/34 , C23C18/36 , H01L21/288 , H01L21/76856 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal alloy capping layer containing a group VIII metal and silicon, carbon, or nitrogen may be used to protect copper interconnects of integrated circuits from oxidation and to prevent the electromigration of copper interconnects while at the same time not effecting the performance of integrated circuit. Methods of incorporating the silicon, carbon, or nitrogen into the group VIII metal to form the metal alloy capping layer are also presented along with methods of electrolessly forming the cap on a metal interconnect line.
摘要翻译：可以使用含有VIII族金属和硅，碳或氮的金属合金覆盖层来保护集成电路的铜互连免受氧化，并且防止铜互连的电迁移，同时不影响集成电路的性能。将硅，碳或氮掺入第VIII族金属以形成金属合金覆盖层的方法也与在金属互连线上无电镀成形帽的方法一起呈现。

27. 发明申请

US20050146034A1 Method to fabricate interconnect structures 有权
标题翻译：制造互连结构的方法
公开(公告)号：US20050146034A1
公开(公告)日：2005-07-07
申请号：US10748106
申请日：2003-12-24
申请人： Tatyana Andreyushchenko , Kenneth Cadien , Paul Fischer , Valery Dubin
发明人： Tatyana Andreyushchenko , Kenneth Cadien , Paul Fischer , Valery Dubin
IPC分类号： H01L21/288 , H01L21/768 , H01L21/4763 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/2885 , H01L21/76844 , H01L21/76849 , H01L21/76856 , H01L21/76873 , H01L21/76877 , H01L21/76888
摘要： A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.
摘要翻译：一种方法包括在包括至少一个接触开口的基板表面上形成阻挡层; 在所述接触开口中形成互连; 并降低阻挡层的导电性。一种方法，包括在包括电介质层和接触开口的衬底表面上形成阻挡层，在接触开口中沉积导电材料，去除足以暴露衬底表面上的阻挡层的导电材料，以及降低导电材料的导电性阻挡层。一种包括电路基板的设备，包括至少一个有源层，包括至少一个接触点，至少一个有源层上的电介质层，介电层表面上的阻挡层，阻挡层的一部分已经被转变从第一电导率到第二不同和降低的电导率，以及耦合到所述至少一个接触点的互连。

28. 发明申请

US20050136654A1 Multiple stage electroless deposition of a metal layer 失效
公开(公告)号：US20050136654A1
公开(公告)日：2005-06-23
申请号：US10744119
申请日：2003-12-22
申请人： Chin-Chang Cheng , Valery Dubin
发明人： Chin-Chang Cheng , Valery Dubin
IPC分类号： B32B15/00 , B32B15/04 , C23C18/16 , C23C18/34 , C23C18/36 , H01L21/288 , H01L21/44 , H01L21/768 , H05K3/24
CPC分类号： H01L21/76846 , C23C18/1651 , C23C18/34 , C23C18/36 , H01L21/288 , H01L21/76838 , H01L21/76849 , H05K3/244 , H05K2203/072 , H05K2203/1476 , Y10T428/12576 , Y10T428/12861
摘要： A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

29. 发明授权

US06271591B1 Copper-aluminum metallization 有权
标题翻译：铜铝金属化
公开(公告)号：US06271591B1
公开(公告)日：2001-08-07
申请号：US09312937
申请日：1999-05-17
申请人： Valery Dubin , Chiu Ting
发明人： Valery Dubin , Chiu Ting
IPC分类号： H01L2348
CPC分类号： H01L23/53233 , H01L21/288 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.
摘要翻译：描述了利用无电铜沉积技术制造铜 - 铝金属化的方法。该方法提供了一种自封装的铜 - 铝金属化结构。

30. 发明授权

US5969422A Plated copper interconnect structure 失效
标题翻译：镀铜互连结构
公开(公告)号：US5969422A
公开(公告)日：1999-10-19
申请号：US857129
申请日：1997-05-15
申请人： Chiu Ting , Valery Dubin
发明人： Chiu Ting , Valery Dubin
IPC分类号： H01L21/768 , H01L23/532 , H01L29/45
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.
摘要翻译：通过在包含催化活性金属如Cu的合金和诸如Ta的难熔金属的种子层上电镀或化学镀Cu或Cu基合金来形成高导电性互连结构。种子层还用作随后镀覆的Cu或Cu基合金的阻挡/粘合层。另一个实施方案包括在沉积种子层之前首先沉积难熔金属阻挡层。

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