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21. 发明申请

US20130146954A1 Method Of Memory Array And Structure Form 审中-公开
标题翻译：存储器阵列和结构形式的方法
公开(公告)号：US20130146954A1
公开(公告)日：2013-06-13
申请号：US13429448
申请日：2012-03-26
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/10876 , H01L27/10885
摘要： The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.
摘要翻译：本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。掩埋位线设置在基板中并沿第二方向延伸。字线设置在基板中沿第一方向延伸。漏极区域设置在未被字线覆盖的有源区域中。电容器设置在基板上并电连接到漏极区域。

22. 发明授权

US08309998B2 Memory structure having a floating body and method for fabricating the same 有权
标题翻译：具有浮体的存储结构及其制造方法
公开(公告)号：US08309998B2
公开(公告)日：2012-11-13
申请号：US13102039
申请日：2011-05-05
申请人： Tzung-Han Lee , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/7841 , H01L27/10802 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.
摘要翻译：提供一种具有浮体的存储器结构，其包括：衬底，其包括有源区域和围绕有源区域的隔离结构;有源区域中的衬底中的第一源极/漏极区域;位于衬底中的第一浮置体第一源极/漏极区域，第一浮体上的第二浮体，第二浮体上的第二源极/漏极区域，以及衬底中的沟槽型栅极结构以及第一浮体旁边。还提供了一种制造具有浮体的存储结构的方法。

23. 发明授权

US07960241B2 Manufacturing method for double-side capacitor of stack DRAM 有权
标题翻译：堆叠DRAM双面电容器制造方法
公开(公告)号：US07960241B2
公开(公告)日：2011-06-14
申请号：US12698322
申请日：2010-02-02
申请人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
发明人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L28/90
摘要： A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.
摘要翻译：堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

24. 发明授权

US07633109B2 DRAM structure and method of making the same 有权
标题翻译： DRAM结构和制作方法
公开(公告)号：US07633109B2
公开(公告)日：2009-12-15
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

25. 发明授权

US07615443B2 Method of forming finFET device 有权
标题翻译：形成finFET器件的方法
公开(公告)号：US07615443B2
公开(公告)日：2009-11-10
申请号：US12030210
申请日：2008-02-13
申请人： Chih-Hao Cheng , Tzung-Han Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879
摘要： The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.
摘要翻译：本发明公开了一种形成finFET器件的方法。在半导体衬底的有源区上形成硬掩模层。硬掩模层的一部分被蚀刻以形成凹部。在凹槽上沉积保形栅极限定层，并执行倾斜角度离子注入工艺。去除栅极限定层的一部分以限定鳍状图案。翅片图案随后转移到硬掩模层。将具有翅片图案的图案化的硬掩模层用作蚀刻掩模，并且蚀刻半导体衬底以形成翅片结构。

26. 发明申请

US20070298567A1 SRAM CELL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US20070298567A1
公开(公告)日：2007-12-27
申请号：US11852185
申请日：2007-09-07
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rem-Hurng Larn
IPC分类号： H01L21/8244
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

27. 发明授权

US07157763B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07157763B2
公开(公告)日：2007-01-02
申请号：US10983140
申请日：2004-11-04
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

28. 发明申请

US20060192241A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060192241A1
公开(公告)日：2006-08-31
申请号：US11066994
申请日：2005-02-25
申请人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
发明人： Tzung-Han Lee , Wen-Jeng Lin , Kuang-Pi Lee , Blue Larn
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/6653
摘要： A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.
摘要翻译：包括衬底，堆叠栅极结构，导电间隔物，氧化物/氮化物/氧化物层，掩埋掺杂区域，控制栅极和绝缘层的非易失性存储器。层叠的栅极结构设置在基板上。堆叠栅极结构包括栅极介电层，选择栅极和盖层。导电间隔物设置在堆叠栅结构的侧壁上。氧化物/氮化物/氧化物层设置在导电间隔物和层叠栅极结构之间以及导电间隔物和衬底之间。掩埋掺杂区域设置在层叠栅极结构的每一侧上的导电间隔物外部的衬底中。控制栅极设置在堆叠的栅极结构上并电连接到导电间隔物。绝缘层设置在掩埋掺杂层和控制栅极之间。

29. 发明授权

US06361928B1 Method of defining a mask pattern for a photoresist layer in semiconductor fabrication 失效
标题翻译：在半导体制造中定义光致抗蚀剂层的掩模图案的方法
公开(公告)号：US06361928B1
公开(公告)日：2002-03-26
申请号：US09578358
申请日：2000-05-24
申请人： Jin-Sheng Yang , Tzung-Han Lee
发明人： Jin-Sheng Yang , Tzung-Han Lee
IPC分类号： G03F740
CPC分类号： G03F7/40
摘要： A method of defining a mask pattern for a photoresist layer in semiconductor fabrication. The method coats a photoresist layer containing an additive on a dielectric layer. The photoresist layer has an opening formed therein. The additive is 2,2′-azo-bis-isobutyronitride (AIBN) or phenyl-azo-triphenylmethane. The photoresist layer is exposed and developed. Then, a hard baking step is performed. A UV curing or a hot curing step is performed on the photoresist layer. As a result, the additive in the photoresist layer reacts to form nitrogen (N2) gas. Nitrogen gas makes the photoresist layer expand. The opening is decreased by the expansion of the photoresist layer. The dielectric layer is etched according to the expanded photoresist layer so that a via or a trench, which is smaller than a conventional one, is formed.
摘要翻译：一种在半导体制造中定义光致抗蚀剂层的掩模图案的方法。该方法在电介质层上涂覆含有添加剂的光致抗蚀剂层。光致抗蚀剂层具有形成在其中的开口。添加剂为2,2'-偶氮双异丁腈（AIBN）或苯基偶氮三苯甲烷。光致抗蚀剂层被曝光和显影。然后，进行硬烘烤步骤。在光致抗蚀剂层上进行UV固化或热固化步骤。结果，光致抗蚀剂层中的添加剂反应形成氮气（N 2）。氮气使光致抗蚀剂层膨胀。通过光致抗蚀剂层的膨胀来减小开口。根据扩展的光致抗蚀剂层蚀刻电介质层，从而形成比常规通孔小的通孔或沟槽。

30. 发明授权

US06331471B1 Method for improving peeling issues during fabrication of integrated circuits 失效
标题翻译：在集成电路制造过程中改善剥离问题的方法
公开(公告)号：US06331471B1
公开(公告)日：2001-12-18
申请号：US09394559
申请日：1999-09-18
申请人： Tzung-Han Lee , Wayne Tan
发明人： Tzung-Han Lee , Wayne Tan
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10808
摘要： A new method for forming integrated circuits is disclosed. The method includes the following procedures. A substrate over which a high integration region and a low integration region beside the high integration region are formed. Then dummy layer is formed on the low integration region. Next, a dielectric layer is formed on the high integration region and the dummy layer on the low integration region. Finally, the dielectric layer is planarized.
摘要翻译：公开了一种形成集成电路的新方法。该方法包括以下步骤。形成高积分区域旁边的高积分区域和低积分区域的基板。然后在低积分区域上形成虚设层。接下来，在高积分区域和低积分区域上的虚设层上形成电介质层。最后，介电层被平坦化。

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