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21. 发明申请

US20130251305A1 FLEXIBLE FIBER TO WAFER INTERFACE 有权
标题翻译：柔性纤维到波形界面
公开(公告)号：US20130251305A1
公开(公告)日：2013-09-26
申请号：US13453027
申请日：2012-04-23
申请人： Tymon Barwicz , Hidetoshi Numata , Yoichi Taira
发明人： Tymon Barwicz , Hidetoshi Numata , Yoichi Taira
IPC分类号： G02B6/12
CPC分类号： G02B6/305 , G02B6/3885 , G02B2006/12173 , G02B2006/12176 , G02B2006/1219
摘要： A fiber to wafer interface system includes an interface device comprising a flexible substrate portion, a flexible cladding portion arranged on the substrate portion, a flexible single-mode waveguide portion arranged on the cladding portion including a substantially optically transparent material, a connector portion engaging a first distal end of the flexible substrate portion, the connector portion operative to engage a portion of an optical fiber ferrule, a wafer portion comprising a single mode waveguide portion arranged on a portion of the wafer, an adhesive disposed between a portion of the single mode waveguide portion of the body portion and the single mode waveguide portion of the wafer portion, the adhesive securing the body portion to the wafer portion.
摘要翻译：光纤到晶片接口系统包括：接口装置，包括柔性基板部分，布置在基板部分上的柔性包层部分，布置在包括基本上光学透明材料的包层部分上的柔性单模波导部分，柔性基板部分的第一远端，连接器部分可操作以接合光纤套圈的一部分，晶片部分包括布置在晶片的一部分上的单模波导部分，粘合剂设置在单模主体部分的波导部分和晶片部分的单模波导部分，将本体部分固定到晶片部分上的粘合剂。

22. 发明申请

US20130156365A1 Fiber to Wafer Interface 失效
标题翻译：光纤到晶圆接口
公开(公告)号：US20130156365A1
公开(公告)日：2013-06-20
申请号：US13331164
申请日：2011-12-20
申请人： Tymon Barwicz , Darrell R. Childers , Dan Kurtz
发明人： Tymon Barwicz , Darrell R. Childers , Dan Kurtz
IPC分类号： G02B6/12
CPC分类号： G02B6/30 , G02B6/1228 , G02B6/125 , G02B6/138
摘要： An interface device includes a body portion having a single-mode waveguide portion including a substantially optically transparent material, a cladding portion defined by channels contacting the waveguide portion, the cladding portion including a substantially optically transparent polymer material, an engagement feature operative to engage a portion of a wafer, and a guide portion operative to engage a portion of an optical fiber ferrule.
摘要翻译：接口装置包括具有单模波导部分的主体部分，其包括基本上光学透明的材料，由与波导部分接触的通道限定的包层部分，包层部分包括基本上光学透明的聚合物材料，接合特征可操作以接合晶片的一部分，以及可操作地接合光纤套圈的一部分的引导部。

23. 发明申请

US20120300534A1 HIGH DENSITY MEMORY DEVICE 有权
标题翻译：高密度存储器件
公开(公告)号：US20120300534A1
公开(公告)日：2012-11-29
申请号：US13570390
申请日：2012-08-09
申请人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
发明人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
IPC分类号： G11C11/00
CPC分类号： G11C11/404 , G11C13/0007 , H01L28/40 , H01L49/003
摘要： A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device.
摘要翻译：一种操作具有介电材料层，过渡金属氧化物层和一组电极的存储器件的方法，每个形成在衬底上，包括在整个电极组上施加电压，从而在过渡金属氧化物层上产生电场，从而能够过渡金属氧化物层进行金属绝缘转变（MIT）以对存储器件执行读或写操作。

24. 发明授权

US08299565B2 Semiconductor nanowires having mobility-optimized orientations 有权
标题翻译：具有移动性优化取向的半导体纳米线
公开(公告)号：US08299565B2
公开(公告)日：2012-10-30
申请号：US13075551
申请日：2011-03-30
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

25. 发明授权

US08105758B2 Microphotonic maskless lithography 有权
标题翻译：微波无掩模光刻
公开(公告)号：US08105758B2
公开(公告)日：2012-01-31
申请号：US11776419
申请日：2007-07-11
申请人： Tymon Barwicz , Milos Popovic
发明人： Tymon Barwicz , Milos Popovic
IPC分类号： G02B6/26 , G02B6/34
CPC分类号： G03F7/70383
摘要： A maskless lithography system and method to expose a pattern on a wafer by propagating a photon beam through a waveguide on a substrate in a plane parallel to a top surface of the wafer.
摘要翻译：一种无掩模光刻系统和方法，通过在平行于晶片顶表面的平面内传播光子束通过衬底上的波导而暴露晶片上的图案。

26. 发明申请

US20110207335A1 Constrained Oxidation of Suspended Micro- and Nano-Structures 有权
标题翻译：悬浮微米和纳米结构的约束氧化
公开(公告)号：US20110207335A1
公开(公告)日：2011-08-25
申请号：US12709981
申请日：2010-02-22
申请人： Tymon Barwicz
发明人： Tymon Barwicz
IPC分类号： H01L21/316
CPC分类号： H01L29/0665 , B81B2203/0109 , B81C1/00833 , B81C2201/0178 , B81C2201/053 , B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/775
摘要： Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.
摘要翻译：提供了用于在氧化期间防止悬浮的微/纳米结构的弯曲/屈曲的技术。一方面，提供一种氧化结构的方法。该方法包括提供具有至少一个悬浮元素的结构，所述悬浮元素选自：微结构，纳米结构及其组合; 围绕包层材料中的至少一个悬挂元件; 以及通过所述包层材料氧化所述至少一个悬浮元件，其中所述包层材料物理地约束并由此防止所述至少一个悬浮元件在氧化期间的变形。

27. 发明申请

US20110107841A1 PIEZORESISTIVE STRAIN SENSOR BASED NANOWIRE MECHANICAL OSCILLATOR 有权
标题翻译：基于感应应变传感器的纳米机械振荡器
公开(公告)号：US20110107841A1
公开(公告)日：2011-05-12
申请号：US12616965
申请日：2009-11-12
申请人： Tymon Barwicz , Hendrik F. Hamann , Levente Klein
发明人： Tymon Barwicz , Hendrik F. Hamann , Levente Klein
IPC分类号： G01L1/18 , G01P15/12
CPC分类号： G01L1/183 , G01P15/097 , G01P15/123 , H03H9/02259 , H03H9/2405
摘要： An apparatus is provided and includes compressed conductive elements that each have independently adjustable dimensions sufficient to provide substantially enhanced piezoresistance to a current flowing across each conductive element with each of the conductive elements subjected to compressive strain, the conductive elements being oscillated in a direction parallel to that of the compressive strain at a defined frequency such that a resistance of the conductive elements to the current is thereby substantially reduced.
摘要翻译：提供了一种装置并且包括压缩的导电元件，每个压缩导电元件具有足够的独立调节尺寸，以足以对流过每个导电元件的电流提供显着增强的压阻，导电元件经受压应变，导电元件在平行于在限定的频率下的压缩应变，使得导电元件对电流的电阻因此显着降低。

28. 发明申请

US20100252814A1 SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS 有权
标题翻译：具有移动优化方位的半导体纳米级
公开(公告)号：US20100252814A1
公开(公告)日：2010-10-07
申请号：US12417796
申请日：2009-04-03
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/12 , H01L21/782
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

29. 发明申请

US20090298269A1 STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：具有层间错位的单晶半导体层的结构在相同的层次上及其制造方法
公开(公告)号：US20090298269A1
公开(公告)日：2009-12-03
申请号：US12538759
申请日：2009-08-10
申请人： Tymon Barwicz , Devendra K. Sadana
发明人： Tymon Barwicz , Devendra K. Sadana
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L21/02551 , H01L27/1203 , H01L27/1207
摘要： A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate.
摘要翻译：提供了含有单晶IV族半导体的半导体衬底。在半导体层的一部分上外延生长单晶格不匹配的IV族半导体合金层，而半导体层的另一部分被掩蔽。调整晶格失配的IV族半导体合金层的组成基本上与单晶化合物半导体层的晶格常数匹配，随后在单晶格子失配的IV族半导体合金层上外延生长。因此，具有IV族半导体层和单晶化合物半导体层的结构设置在同一半导体衬底上。诸如硅器件的IV族半导体器件和诸如具有激光发射能力的GaAs器件的化合物半导体器件可以形成在半导体衬底的相同的光刻层上。

30. 发明申请

US20090067463A1 STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：US20090067463A1
公开(公告)日：2009-03-12
申请号：US11851858
申请日：2007-09-07
申请人： Tymon Barwicz , Devendra K. Sadana
发明人： Tymon Barwicz , Devendra K. Sadana
IPC分类号： H01S5/20 , H01L21/20 , H01L29/267
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L21/02551 , H01L27/1203 , H01L27/1207
摘要： A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate.

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