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21. 发明授权

US08605184B2 Pixel circuit, solid-state image pickup device, and camera 有权
标题翻译：像素电路，固态摄像装置和相机
公开(公告)号：US08605184B2
公开(公告)日：2013-12-10
申请号：US13126790
申请日：2009-11-25
申请人： Toshiyuki Nishihara
发明人： Toshiyuki Nishihara
IPC分类号： H04N5/335
CPC分类号： H04N5/3745 , H01L27/14609 , H04N5/3559
摘要： A pixel circuit has first, second, and third field effect transistors integrated and connected in series from a photoelectric conversion element to a side of an amplifier circuit. The first and second field effect transistors have gate electrodes to be simultaneously collectively driven. A threshold voltage of the first field effect transistor is set to be higher than that of the second field effect transistor. As the gate electrodes are driven step by step, electrons generated by the photoelectric conversion element and transferred via the first field effect transistor are accumulated in a channel region of the second field effect transistor. The electrons accumulated in the channel region are transferred to an input of the amplifier circuit via the third field effect transistor.
摘要翻译：像素电路具有从光电转换元件串联连接到放大器电路侧的第一，第二和第三场效应晶体管。第一和第二场效应晶体管具有同时共同驱动的栅电极。第一场效应晶体管的阈值电压被设定为高于第二场效应晶体管的阈值电压。随着门电极逐步驱动，由光电转换元件产生并通过第一场效应晶体管传送的电子被累积在第二场效应晶体管的沟道区中。积累在沟道区中的电子经由第三场效应晶体管传送到放大器电路的输入端。

22. 发明授权

US08554982B2 Storage device and information processing system 有权
标题翻译：存储设备和信息处理系统
公开(公告)号：US08554982B2
公开(公告)日：2013-10-08
申请号：US11251867
申请日：2005-10-18
申请人： Toshiyuki Nishihara , Yoshio Sakai
发明人： Toshiyuki Nishihara , Yoshio Sakai
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0246 , G06F3/0641 , G06F12/00 , G06F12/0223 , G06F12/08 , G06F12/0813 , G06F12/0866 , G06F12/10 , G06F12/1009 , G06F12/1081 , G06F13/28 , G06F2212/1024 , G06F2212/2022 , G06F2212/2024 , G06F2212/7201 , G11C8/08 , G11C11/22 , Y02D10/13
摘要： A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.
摘要翻译：一种存储装置，其能够对未选择的数据进行冗余写入操作，并且能够将页面的布置优化为具有用于重写的高效率的状态，其中所述存储装置具有第一存储器单元，具有不同访问的第二存储器单元第一存储器的速度以及控制电路，其中控制电路具有在读取或重写中具有不同访问速度的第一存储器单元和第二存储器单元之间以两种方式及时移动存储的数据的功能。

23. 发明授权

US08488034B2 Imaging device and camera system including sense circuits to make binary decision 有权
标题翻译：成像装置和相机系统包括感应电路进行二进制决定
公开(公告)号：US08488034B2
公开(公告)日：2013-07-16
申请号：US12846285
申请日：2010-07-29
申请人： Toshiyuki Nishihara
发明人： Toshiyuki Nishihara
IPC分类号： H04N3/14 , H04N5/335 , H04L27/148
CPC分类号： H04N5/359 , G01J1/44 , H01L27/14612 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/14645 , H01L27/1469 , H04N5/3355 , H04N5/3535 , H04N5/3537 , H04N5/357 , H04N5/361 , H04N5/365 , H04N5/374 , H04N5/37452 , H04N5/37455 , H04N5/378
摘要： An imaging device includes: a pixel array section having an array of pixels each of which has a photoelectric converting device and outputs an electric signal according to an input photon; a sense circuit section having a plurality of sensor circuits each of which makes binary decision on whether there is a photon input to a pixel in a predetermined period upon reception of the electric signal therefrom; and a decision result IC section which integrates decision results from the sense circuits, pixel by pixel or for each group of pixels, multiple times to generate imaged data with a gradation, the decision result IC section including a count circuit which performs a count process to integrate the decision results from the sense circuits, and a memory for storing a counting result for each pixel from the count circuit, the plurality of sense circuits sharing the count circuit for integrating the decision results.
摘要翻译：一种成像装置，包括：具有像素阵列的像素阵列部，每个像素阵列具有光电转换装置，并根据输入光子输出电信号; 感测电路部分，具有多个传感器电路，每个传感器电路在从其接收到电信号时在预定周期内是否存在对像素的光子输入的二进制决定; 以及决定结果IC部，其对来自感测电路的逐个像素或每组像素的判定结果进行多次积分，以生成具有灰度的成像数据，所述判定结果IC部包括执行计数处理的计数电路集成来自感测电路的判定结果，以及存储器，用于存储来自计数电路的每个像素的计数结果，多个感测电路共享用于积分判定结果的计数电路。

24. 外观设计

USD669821S1 Motorcycle 有权
公开(公告)号：USD669821S1
公开(公告)日：2012-10-30
申请号：US29395700
申请日：2012-03-13
申请人： Toshiyuki Nishihara , Takumi Uemoto
设计人： Toshiyuki Nishihara , Takumi Uemoto

25. 发明授权

US08285916B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US08285916B2
公开(公告)日：2012-10-09
申请号：US11446367
申请日：2006-06-05
申请人： Toshiyuki Nishihara , Takeshi Ishimoto
发明人： Toshiyuki Nishihara , Takeshi Ishimoto
IPC分类号： G06F12/02
CPC分类号： G11C16/102 , G06F3/061 , G06F3/0662 , G06F3/0679 , G06F12/0246 , G06F2212/7201
摘要： A storage device, enabling elimination of redundant write operations of non-selected data and enabling optimization of arrangement of pages to a state efficient for rewriting, having two flash memories which can be accessed in parallel, a page register for acquiring data in parallel from the flash memories and temporarily storing the same, and a control circuit having a built-in RAM in which is constructed an address conversion table for managing correspondence between logical addresses and physical addresses in units of data stored in parallel in the page register, wherein data is rewritten by updating of the address conversion table and additional writing into a storage medium.
摘要翻译：一种存储装置，能够消除非选择数据的冗余写入操作，并且能够优化页面排列到有效重写的状态，具有可并行访问的两个闪速存储器，用于从闪速存储器并临时存储它们，以及具有内置RAM的控制电路，其中构成有用于管理逻辑地址和物理地址之间的对应关系的地址转换表，其以页寄存器中并行存储的数据为单位，其中数据是通过更新地址转换表并将其附加写入存储介质来重写。

26. 发明授权

US08208053B2 Imaging device, camera, control method for imaging device, and computer program 有权
标题翻译：成像设备，相机，成像设备的控制方法和计算机程序
公开(公告)号：US08208053B2
公开(公告)日：2012-06-26
申请号：US12457680
申请日：2009-06-18
申请人： Toshiyuki Nishihara
发明人： Toshiyuki Nishihara
IPC分类号： H04N9/64 , H04N3/14 , H04N5/335
CPC分类号： H04N5/3535
摘要： An imaging device includes: plural pixel blocks with a predetermined number of pixel circuits of respective plural blocks set as one unit, the plural blocks being obtained by dividing a pixel area formed by arraying plural pixel circuits, which convert incident light into charges according to photoelectric conversion, in a matrix shape; and a selection control unit that selects desired ones of the pixel blocks and collectively executes reset control for discharging charges accumulated by the respective pixel circuits in the selected pixel blocks, wherein the selection control unit changes timing for executing the reset control for each of the selected pixel blocks and allocates different charge accumulating times to the pixel circuits.
摘要翻译：一种成像装置包括：具有设定为一个单位的多个块的预定数量的像素电路的多个像素块，所述多个块通过将由多个像素电路排列形成的像素区域分割而获得，该像素电路根据光电转换入射光转换成矩阵形状; 以及选择控制单元，其选择所需的像素块并且共同地执行用于对所选择的像素块中的各个像素电路累积的电荷进行放电的复位控制，其中，所述选择控制单元改变为所选择的像素块中的每一个执行复位控制的定时像素块并且向像素电路分配不同的电荷累积时间。

27. 发明申请

US20110242385A1 Solid-state imaging device and camera system 有权
标题翻译：固态成像装置和相机系统
公开(公告)号：US20110242385A1
公开(公告)日：2011-10-06
申请号：US12929837
申请日：2011-02-18
申请人： Toshiyuki Nishihara
发明人： Toshiyuki Nishihara
IPC分类号： H04N5/335 , H01L27/146
CPC分类号： H04N5/378 , H04N5/374
摘要： A solid-state imaging device includes: a pixel circuit including a photoelectric conversion device and an amp device that outputs electric charges, which are photoelectrically converted by the photoelectric conversion device, through electric potential modulation of an output signal line; and a reading section including an AD (analog digital) conversion circuit that compares an output level of the signal line with a reference signal which changes with a regular slope and digitalizes an output signal on the basis of a timing at which a previously-defined relationship is satisfied between the output signal and the reference signal.
摘要翻译：固态成像装置包括：通过输出信号线的电位调制，包括光电转换装置和放大装置的像素电路，其输出由光电转换装置光电转换的电荷; 以及读取部分，其包括AD（模拟数字）转换电路，其将信号线的输出电平与以规则斜率变化的参考信号进行比较，并且基于预定关系的定时对输出信号进行数字化在输出信号和参考信号之间满足。

28. 发明授权

US07890695B2 Storage device, computer system, and data writing method 有权
标题翻译：存储设备，计算机系统和数据写入方式
公开(公告)号：US07890695B2
公开(公告)日：2011-02-15
申请号：US12662153
申请日：2010-04-01
申请人： Toshiyuki Nishihara , Daisuke Yoshioka
发明人： Toshiyuki Nishihara , Daisuke Yoshioka
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G11C16/12 , G06F12/0888 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/0483 , Y02D10/13
摘要： A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.
摘要翻译：一种存储装置，包括提供存储介质的闪速存储器件，用于闪速存储器件的高速缓存存储器和控制电路。在存储装置中，基于写命令和提供的地址信息，控制电路选择闪存装置或高速缓冲存储器作为输入数据的写入目的地。

29. 发明申请

US20070165468A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070165468A1
公开(公告)日：2007-07-19
申请号：US11716710
申请日：2007-03-12
申请人： Toshiyuki Nishihara , Yoshio Sakai
发明人： Toshiyuki Nishihara , Yoshio Sakai
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/846 , G11C2029/1208
摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.
摘要翻译：一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器的缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域，其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储更宽范围的有缺陷的存储器的地址。为此，可以有效地修复随机发生的缺陷。

30. 发明授权

US07236413B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07236413B2
公开(公告)日：2007-06-26
申请号：US11143575
申请日：2005-06-03
申请人： Toshiyuki Nishihara
发明人： Toshiyuki Nishihara
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A semiconductor memory device, wherein an access to a first memory portion is made by referring to an address transformation table stored in a second memory portion, so that an access to a defective block is prevented; the second memory portion and the first memory portion are mounted on the same semiconductor chip, so that a part or all of address data input from outside the semiconductor chip can be made corresponding to an address of the second memory portion and input to the second memory portion without executing any calculation, and a stored pointer can be taken out at a high speed; and an access can be made to a memory at a high speed by following the address transformation table.
摘要翻译：一种半导体存储器件，其中通过参考存储在第二存储器部分中的地址变换表来进行对第一存储器部分的访问，从而防止对缺陷块的访问; 第二存储器部分和第一存储器部分安装在相同的半导体芯片上，使得可以对应于第二存储器部分的地址进行从半导体芯片的外部输入的部分或全部地址数据，并将其输入到第二存储器部分而不执行任何计算，并且可以高速地取出存储的指针; 并且可以通过跟随地址变换表来高速地访问存储器。

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