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    • 23. 发明申请
    • Ferroelectric memory
    • 铁电存储器
    • US20050018468A1
    • 2005-01-27
    • US10919403
    • 2004-08-17
    • Toshiyuki Honda
    • Toshiyuki Honda
    • H01L27/105G11C7/00G11C11/22H01L21/02H01L21/8246H01L27/10H01L27/115
    • H01L27/11502G11C11/22H01L27/11507H01L28/55
    • A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells. Bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction. Cuts are formed at positions of the plate lines near the bit line contacts. The active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.
    • 铁电存储器具有多个存储单元,每个存储单元具有以矩阵形式布置的晶体管和铁电电容器。 板条线在多个存储单元之间的字线方向上彼此相邻的存储单元的铁电电容器之间的字线方向上延伸。 每个用于连接位线的位线触点和晶体管的有源区域被放置在位线方向上彼此相邻的板线之间的区域中以及在字线方向上彼此相邻的铁电电容器之间的区域中。 在位线接触点附近的板条的位置处形成切口。 多个存储单元的晶体管的有源区域在与字线方向和位线方向相交的方向上延伸。
    • 24. 发明授权
    • Ferroelectric memory
    • 铁电存储器
    • US06784468B2
    • 2004-08-31
    • US09988817
    • 2001-11-20
    • Toshiyuki Honda
    • Toshiyuki Honda
    • H01L2710
    • H01L27/11502G11C11/22H01L27/11507H01L28/55
    • A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells. Bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction. Cuts are formed at positions of the plate lines near the bit line contacts. The active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.
    • 铁电存储器具有多个存储单元,每个存储单元具有以矩阵形式布置的晶体管和铁电电容器。 板条线在多个存储单元之间的字线方向上彼此相邻的存储单元的铁电电容器之间的字线方向上延伸。 每个用于连接位线的位线触点和晶体管的有源区域被放置在位线方向上彼此相邻的板线之间的区域中以及在字线方向上彼此相邻的铁电电容器之间的区域中。 在位线接触点附近的板条的位置处形成切口。 多个存储单元的晶体管的有源区域在与字线方向和位线方向相交的方向上延伸。
    • 26. 发明授权
    • Semiconductor device
    • 半导体器件
    • US5594697A
    • 1997-01-14
    • US494827
    • 1995-06-26
    • Hiroshige HiranoToshiyuki Honda
    • Hiroshige HiranoToshiyuki Honda
    • G11C5/14G11C7/06G11C16/26
    • G11C7/067G11C16/26G11C5/143G11C2207/063
    • A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.
    • 半导体器件包括非易失性存储单元和电流检测型读出放大器,用于检测流过存储单元的数据线的电流。 半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。 感测放大器包括用于响应于响应于第一电压检测信号的第二电压检测信号而将电源电压上的电平感测电流的相关特性切换到更高的元件。 因此,可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。
    • 28. 发明授权
    • Nonvolatile storage device, memory controller, and defective region detection method
    • 非易失性存储装置,存储器控制器和缺陷区域检测方法
    • US09092361B2
    • 2015-07-28
    • US11995600
    • 2006-07-13
    • Toshiyuki HondaKunihiro MakiShigekazu Kogita
    • Toshiyuki HondaKunihiro MakiShigekazu Kogita
    • G06F11/00G06F11/10
    • G06F11/1068
    • It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.
    • 可以精确地检测在闪速存储器中造成夹具缺陷的物理块,从而限制物理块的使用。 通过在ECC错误记录中记录生成物理块错误和物理擦除历史的历史,判断发生的错误是偶然的还是由固定缺陷引起的。 在第一次读取错误发生后,通过物理擦除写入的数据没有引起错误时,第一个错误是偶然的,如果引起另一个错误,则判断该错误是由于一个夹具缺陷引起的。 通过使用这样的ECC错误记录,可以准确地判断误差是偶然的还是由夹具缺陷引起的。 通过消除被认为具有夹具缺陷的物理块的使用,可以减少读取错误。
    • 30. 发明授权
    • Memory controller and non-volatile storage device
    • 内存控制器和非易失性存储设备
    • US08656252B2
    • 2014-02-18
    • US13463170
    • 2012-05-03
    • Hirokazu SoToshiyuki Honda
    • Hirokazu SoToshiyuki Honda
    • G11C29/00
    • H03M13/2906G06F11/1044G06F11/108H03M13/05H03M13/1515H03M13/27H03M13/2927H03M13/3715H03M13/3738H03M13/6561
    • A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.
    • 非易失性存储设备包括用于存储数据的一个或多个非易失性存储器和用于执行非易失性存储器的控制的存储器控​​制器。 非易失性存储器包括作为擦除单元的多个块,并且该块包括作为数据的写入单元的多个页面,每个块中存在至少一组页面,其包括至少两个页面 共享一个字线。 存储器控制器配置多个纠错组,每个纠错组包括作为用于存储数据的页面的至少一个数据页面和用于存储用于错误校正数据页面计算的代码的至少一个纠错码页面,并且分配 关于相同纠错组中的每个数据页和错误校正页的单独字线的页面。