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21. 发明授权

US06829574B1 Logic emulation module and logic emulation board 有权
标题翻译：逻辑仿真模块和逻辑仿真板
公开(公告)号：US06829574B1
公开(公告)日：2004-12-07
申请号：US09328800
申请日：1999-06-09
申请人： Hiroshi Ito , Akira Yamagiwa , Nobuaki Ejima , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura
发明人： Hiroshi Ito , Akira Yamagiwa , Nobuaki Ejima , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura
IPC分类号： G06F9455
CPC分类号： G06F17/5027 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis. Also disclosed here is an upgraded module structure permitting a multiple-stage module setup together with an advanced cooling structure for modules.
摘要翻译：这里公开了一种用于逻辑仿真的改进的逻辑模块以及经过逻辑验证的增强型逻辑仿真板。逻辑模块具有能够编程逻辑的多个可编程LSI和能够编程连接的多个开关LSI，LSI安装在板的一侧或两侧。板的外围部分携带用于与外部电连接的连接器。有两种类型的数据线：将连接器直接耦合到可编程LSI的数据线，以及通过开关LSI将连接器连接到可编程LSI的那些。可编程和开关式LSI构成了一种交叉连接装置。逻辑仿真板具有用于连接到逻辑仿真模块的连接器，并且用于支持用于开发的LSI的接地。连接器和焊盘的引脚是以一对一的方式相互连接的。这里还公开了一种升级的模块结构，允许多级模块与模块的先进冷却结构一起设置。

22. 发明授权

US06580295B2 Signal transmission system 有权
标题翻译：信号传输系统
公开(公告)号：US06580295B2
公开(公告)日：2003-06-17
申请号：US09777895
申请日：2001-02-07
申请人： Toshitsugu Takekuma , Akira Yamagiwa , Takashi Moriyama , Ryoichi Kurihara
发明人： Toshitsugu Takekuma , Akira Yamagiwa , Takashi Moriyama , Ryoichi Kurihara
IPC分类号： H03K1906
CPC分类号： G06F13/4077
摘要： A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.
摘要翻译：信号传输系统包括：第一电路块，具有用于产生第一信号的第一输出电路;多个第二电路块，每个第二电路块包括用于接收第一信号的第一接收电路;以及连接在第一电路块和第二电路块之间的传输线电路块，其中所述第一电路块还包括用于产生第二信号的第二输出电路，并且其中每个所述第二电路块还包括用于接收所述第二信号的第二接收电路，所述第一接收电路同步地锁存所述第一信号利用第二信号，消除由于电路之间的信号的传播延迟引起的信号发送和接收中的不成功。

23. 发明授权

US06496886B1 Directional coupling bus system using printed board 失效
标题翻译：使用印刷板的定向耦合总线系统
公开(公告)号：US06496886B1
公开(公告)日：2002-12-17
申请号：US09429441
申请日：1999-10-28
申请人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
发明人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
IPC分类号： H01P518
CPC分类号： H01P5/185 , H01P5/187 , H05K1/0228 , H05K1/023 , H05K1/0239 , H05K3/4623 , H05K2201/09236 , H05K2201/09845 , H05K2201/10689
摘要： In a printed board mounting method using a directional coupling bus for a high-speed data transfer, multi-bit data are transferred between nodes at a low cost. For this purpose, to transfer multi-bit data by directional coupling, a one-bit multi-coupling wiring network is vertically configured in a multilayered printed board. This minimizes the width of an area occupied by each bit along a wiring direction of the board to thereby implement a multi-bit configuration.
摘要翻译：在使用用于高速数据传输的定向耦合总线的印刷电路板安装方法中，以比较低的成本在节点之间传送多位数据。为此，为了通过定向耦合传输多位数据，在多层印刷电路板中垂直配置一位多耦合布线网络。这使得沿着板的布线方向的每个位占据的面积的宽度最小化，从而实现多位配置。

24. 发明授权

US06266242B1 Circuit module and information processing apparatus 有权
标题翻译：电路模块及信息处理装置
公开(公告)号：US06266242B1
公开(公告)日：2001-07-24
申请号：US09557161
申请日：2000-04-25
申请人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
发明人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
IPC分类号： H05K720
CPC分类号： G06F1/206 , G06F1/20 , G06F1/203 , H01L23/36 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/16225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a high heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.
摘要翻译：本发明提供一种信息处理装置，其可以设计成小而薄的小型和薄型CPU模块，其具有高的散热效果并且适合于此。 CPU模块包括处理器，电连接到外部的连接器，用于控制处理器和连接器之间的信号传送的系统控制电路，以及印刷电路板，处理器，连接器和系统控制电路被安装。 CPU模块还提供一个散热片，其一面与印刷电路板粘贴，另一侧基本上是平面的。印刷板具有形成在其中的空腔，使得处理器可以以裸芯片状态装配在空腔中。裸芯片的一侧与散热板接合。

25. 发明授权

US06211703B1 Signal transmission system 失效
公开(公告)号：US06211703B1
公开(公告)日：2001-04-03
申请号：US08869890
申请日：1997-06-05
申请人： Toshitsugu Takekuma , Akira Yamagiwa , Takashi Moriyama , Ryoichi Kurihara
发明人： Toshitsugu Takekuma , Akira Yamagiwa , Takashi Moriyama , Ryoichi Kurihara
IPC分类号： H03K19003
CPC分类号： G06F13/4077
摘要： A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.

26. 发明授权

US06172517B2 Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission 失效
标题翻译：信号发送装置，电路块和适合快速信号传输的集成电路
公开(公告)号：US06172517B2
公开(公告)日：2001-01-09
申请号：US09084017
申请日：1998-05-26
申请人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa
发明人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa
IPC分类号： H03K1716
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
摘要翻译：信号发送电路包括一个或多个具有驱动电路和块内传输线的电路块，用于发送由驱动电路产生的信号，一个或多个电路块具有接收电路和块内传输线，用于发送信号到所述接收电路，以及主块间传输线，用于在两个驱动和接收电路块之间传播信号。块间传输线在一或两端由一个或两个具有与块间传输线本身基本上相同的阻抗的电阻终止。块内传输线路中的每一个被提供有电阻元件，其电阻等于或接近于通过从块内传输线路的阻抗减去块间传输线路的阻抗的一半导出的值，降低信号幅度并抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

27. 发明授权

US5818253A Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission 失效
公开(公告)号：US5818253A
公开(公告)日：1998-10-06
申请号：US773753
申请日：1996-12-24
申请人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa
发明人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C11/401 , H03K19/0175 , H04B3/02 , H04L25/02 , H05K1/02 , H05K1/14 , H03K17/16
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

28. 发明授权

US5767695A Fast transmission line implemented with receiver, driver, terminator and IC arrangements 失效
公开(公告)号：US5767695A
公开(公告)日：1998-06-16
申请号：US747208
申请日：1996-11-12
申请人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa , Kenji Kashiwagi , Masao Inoue
发明人： Toshitsugu Takekuma , Ryoichi Kurihara , Akira Yamagiwa , Kenji Kashiwagi , Masao Inoue
IPC分类号： G06F13/40 , H04L25/02 , H03K17/16
CPC分类号： G06F13/4086 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

29. 发明授权

US5668834A Signal transmitting device suitable for fast signal transmission including an arrangement to reduce signal amplitude in a second stage transmission line 失效
标题翻译：适用于快速信号传输的信号发射装置，包括用于降低第二级传输线路中的信号幅度的装置
公开(公告)号：US5668834A
公开(公告)日：1997-09-16
申请号：US388990
申请日：1995-02-15
申请人： Toshitsugu Takekuma , Akira Yamagiwa , Ryoichi Kurihara
发明人： Toshitsugu Takekuma , Akira Yamagiwa , Ryoichi Kurihara
IPC分类号： G06F13/40 , H04L25/02 , H05K1/02 , H05K1/14 , H04B1/40 , H03K17/16 , H03K19/0175
CPC分类号： H04L25/0278 , G06F13/4072 , H04L25/028 , H04L25/0292 , H04L25/0298 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting device includes a transmitting circuit block having a driving circuit connected to a main transmission line for driving a signal and an intra-block transmission line for transmitting a signal sent from the driving circuit to the main transmission line. The device also includes a receiving circuit block having a transmitting/receiving circuit connected to the main transmission line for receiving a signal inputted from said main transmission line and outputting the received signal to a next stage, an intra-block transmission line for transmitting a signal input from the main transmission line to the transmitting/receiving circuit, a receiving circuit for receiving an output signal from the transmitting/receiving circuit, and a next state intra-block transmission line to enable high-speed signal transmission, the main transmission line includes a termination resistor having s resistance equal to an impedance of the main transmission line and the intra-block transmission line includes an element having a resistance substantially equal to a value derived by subtracting a half of the impedance value of the main transmission line from an impedance value of the intra-block transmission line also, to improve transmission speed along the next-stage intra-block transmission line, a termination resistor is provided from the next-stage intra-block transmission line and the transmitting/receiving circuit and the next-stage intra-block transmission line to produce a voltage drop thereacross.
摘要翻译：信号发送装置包括具有连接到用于驱动信号的主传输线的驱动电路和用于将从驱动电路发送的信号发送到主传输线的块内传输线的发送电路块。该装置还包括具有连接到主传输线的发送/接收电路的接收电路块，用于接收从所述主传输线输入的信号并将接收信号输出到下一级，用于发送信号的块内传输线从主传输线到发送/接收电路的输入，用于从发送/接收电路接收输出信号的接收电路和用于实现高速信号传输的下一状态块内传输线，主传输线包括具有等于主传输线和块内传输线的阻抗的电阻的终端电阻包括具有基本上等于通过从阻抗减去主传输线的阻抗值的一半导出的值的电阻的元件块内传输线路的值也可以提高下一代传输线路的传输速度，从下一级块内传输线路和发送/接收电路和下一级块内传输线路提供终端电阻以产生一个电压降。

30. 发明授权

US06780677B2 Process for mounting electronic device and semiconductor device 失效
公开(公告)号：US06780677B2
公开(公告)日：2004-08-24
申请号：US10224339
申请日：2002-08-21
申请人： Satoshi Imasu , Ikuo Yoshida , Tetsuya Hayashida , Akira Yamagiwa , Shinobu Takeura
发明人： Satoshi Imasu , Ikuo Yoshida , Tetsuya Hayashida , Akira Yamagiwa , Shinobu Takeura
IPC分类号： H01L2144
CPC分类号： H05K1/111 , H01L21/563 , H01L23/13 , H01L23/24 , H01L23/49811 , H01L23/5383 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/1134 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/16225 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2225/1023 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H05K1/0271 , H05K1/114 , H05K3/3436 , H05K3/4007 , H05K3/4602 , H05K2201/0133 , H05K2201/091 , H05K2201/09472 , H05K2201/09536 , H05K2201/0959 , H05K2201/10674 , H05K2203/1581 , Y02P70/611 , H01L2924/00014 , H01L2224/13099 , H01L2924/00012 , H01L2924/01082 , H01L2924/00
摘要： An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

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