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21. 发明授权

US06555891B1 SOI hybrid structure with selective epitaxial growth of silicon 有权
公开(公告)号：US06555891B1
公开(公告)日：2003-04-29
申请号：US09690674
申请日：2000-10-17
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

22. 发明授权

US06509611B1 Method for wrapped-gate MOSFET 失效
标题翻译：封装栅极MOSFET的方法
公开(公告)号：US06509611B1
公开(公告)日：2003-01-21
申请号：US09961010
申请日：2001-09-21
申请人： Byeongju Park , Toshiharu Furukawa , Jack A. Mandelman
发明人： Byeongju Park , Toshiharu Furukawa , Jack A. Mandelman
IPC分类号： H01L2994
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66545 , H01L29/66795 , H01L29/78618
摘要： A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the “body-to-source” voltage.
摘要翻译：包裹栅极晶体管包括具有上表面和彼此相对的第一和第二侧表面的衬底。源极和漏极区域形成在衬底中，其间具有沟道区域。沟道区域从衬底的第一侧表面延伸到第二侧表面。在基板上形成栅介电层。栅极电极形成在栅极电介质层上，以覆盖来自上表面和第一和第二侧表面的沟道区域，栅电介质在其间。衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛，并且具有包括第一和第二侧表面的四个侧表面。源极和漏极区域形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

23. 发明授权

US08300452B2 Structure and method for improving storage latch susceptibility to single event upsets 有权
标题翻译：用于改善单个事件扰乱的存储锁存敏感性的结构和方法
公开(公告)号：US08300452B2
公开(公告)日：2012-10-30
申请号：US13050052
申请日：2011-03-17
申请人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/00
CPC分类号： H01L27/11 , G11C11/4125 , H01L27/0921 , H01L27/1104 , H01L29/66181 , H03K3/0375
摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
摘要翻译：数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

24. 发明申请

US20090001481A1 DIGITAL CIRCUITS HAVING ADDITIONAL CAPACITORS FOR ADDITIONAL STABILITY 审中-公开
标题翻译：具有附加电容器的数字电路用于额外的稳定性
公开(公告)号：US20090001481A1
公开(公告)日：2009-01-01
申请号：US11768270
申请日：2007-06-26
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L27/105 , H01L21/8238
CPC分类号： H01L27/0733 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L28/40
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.
摘要翻译：半导体结构及其形成方法。半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。第一和第二源/漏区掺杂相同的掺杂极性。半导体结构还包括在半导体衬底中的第一掺杂区域。第一掺杂区域位于STI区域的第一侧壁和底壁上。第一掺杂区域与第二源极/漏极区域直接物理接触。第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。

25. 发明授权

US07397692B1 High performance single event upset hardened SRAM cell 有权
标题翻译：高性能单事件硬化SRAM单元
公开(公告)号：US07397692B1
公开(公告)日：2008-07-08
申请号：US11612809
申请日：2006-12-19
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.
摘要翻译：一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入，第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。

26. 发明授权

US06614074B2 Grooved planar DRAM transfer device using buried pocket 失效
标题翻译：凹槽平面DRAM传输装置采用埋式口袋
公开(公告)号：US06614074B2
公开(公告)日：2003-09-02
申请号：US09092749
申请日：1998-06-05
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.
摘要翻译：一种带槽的平面DRAM传输装置，其具有形成在位于源极和漏极区域之间的衬底的沟槽中的带槽门。带槽门具有侧壁部分和限定其上的通道的底部部分。底部包括掺杂的凹穴，使得底部上的阈值电压Vt基本上小于侧壁部分上的Vt，使得侧壁部分主要控制通过该装置的电流。

27. 发明授权

US07521776B2 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
标题翻译：使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
公开(公告)号：US07521776B2
公开(公告)日：2009-04-21
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

28. 发明授权

US07081387B2 Damascene gate multi-mesa MOSFET 失效
标题翻译：镶嵌门多台面MOSFET
公开(公告)号：US07081387B2
公开(公告)日：2006-07-25
申请号：US10918949
申请日：2004-08-16
申请人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
发明人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
摘要翻译：公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法，例如气相掺杂或等离子体掺杂时。所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。

29. 发明授权

US06818952B2 Damascene gate multi-mesa MOSFET 有权
公开(公告)号：US06818952B2
公开(公告)日：2004-11-16
申请号：US10262190
申请日：2002-10-01
申请人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
发明人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
IPC分类号： H01L2701
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

30. 发明授权

US06635543B2 SOI hybrid structure with selective epitaxial growth of silicon 失效
标题翻译：具有硅选择性外延生长的SOI混合结构
公开(公告)号：US06635543B2
公开(公告)日：2003-10-21
申请号：US10335652
申请日：2002-12-31
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： A01L21331
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.
摘要翻译：一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。衬垫层形成在硅层上。焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。绝缘垫片形成在沟槽的侧壁上。在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。电子器件可以形成在沟槽的外延硅内。这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

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