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21. 发明申请

US20070228510A1 SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 有权
标题翻译：通过SiO 2的液相沉积沉积分离膜
公开(公告)号：US20070228510A1
公开(公告)日：2007-10-04
申请号：US11760477
申请日：2007-06-08
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区与氧化物。通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

22. 发明申请

US20080040696A1 Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2 审中-公开
标题翻译：通过液相沉积SiO 2填充的浅沟槽隔离的设计结构
公开(公告)号：US20080040696A1
公开(公告)日：2008-02-14
申请号：US11875069
申请日：2007-10-19
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045 , H01L21/76224
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO2). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate. By selectively depositing the oxide so that the active areas are not covered with the oxide, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：设计结构体现在用于设计，制造或测试其中设计结构包括填充有液相沉积二氧化硅（LPD-SiO 2）的浅沟槽隔离物的设计的机器可读介质中。浅沟槽隔离区用于隔离在绝缘体上硅（SOI）衬底上形成的两个有源区。通过选择性地沉积氧化物使得有源区域不被氧化物覆盖，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

23. 发明申请

US20070184647A1 Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes 审中-公开
标题翻译：集成电路芯片利用由碳纳米管形成的定向圆柱形空隙的介电层
公开(公告)号：US20070184647A1
公开(公告)日：2007-08-09
申请号：US11735988
申请日：2007-04-16
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/4763
CPC分类号： B82Y10/00 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.
摘要翻译：集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。优选地，通过首先形成垂直于集成电路晶片的表面的多个相对长的薄碳纳米管，在围绕碳纳米管的表面上沉积常规电介质，然后除去碳纳米管以产生空隙来形成空隙。由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。用于导体的电介质中形成的凹陷衬有非共形绝缘膜以密封空隙。使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

24. 发明申请

US20060022221A1 Integrated circuit chip utilizing oriented carbon nanotube conductive layers 失效
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20060022221A1
公开(公告)日：2006-02-02
申请号：US10901858
申请日：2004-07-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L29/768
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

25. 发明申请

US20080042287A1 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 失效
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20080042287A1
公开(公告)日：2008-02-21
申请号：US11924894
申请日：2007-10-26
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L23/52
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

26. 发明申请

US20070048879A1 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 有权
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20070048879A1
公开(公告)日：2007-03-01
申请号：US11552771
申请日：2006-10-25
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

27. 发明申请

US20060128137A1 Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes 失效
标题翻译：集成电路芯片利用由碳纳米管形成的具有取向的圆柱形空隙的电介质层
公开(公告)号：US20060128137A1
公开(公告)日：2006-06-15
申请号：US11008800
申请日：2004-12-09
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/4763
CPC分类号： B82Y10/00 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.
摘要翻译：集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。优选地，通过首先通过在表面上沉积常规电介质以填充碳纳米管之间的区域，然后通过将碳纳米管去除以形成多个相对较长的薄碳纳米管，形成集成电路晶片的表面，形成空隙产生代替碳纳米管的空隙。由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

28. 发明申请

US20070215874A1 Layout and process to contact sub-lithographic structures 有权
标题翻译：接触亚光刻结构的布局和工艺
公开(公告)号：US20070215874A1
公开(公告)日：2007-09-20
申请号：US11378492
申请日：2006-03-17
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam
IPC分类号： H01L23/58
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/76885 , H01L21/76895 , H01L23/528 , H01L2224/06 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
摘要翻译：一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧第二结构的接触着陆段。用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

29. 发明申请

US20060154463A1 WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING 有权
标题翻译：选择性金属镀层形成的接线图
公开(公告)号：US20060154463A1
公开(公告)日：2006-07-13
申请号：US10905590
申请日：2005-01-12
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/3205
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
摘要翻译：使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

30. 发明申请

US20060073682A1 LOW-K DIELECTRIC MATERIAL BASED UPON CARBON NANOTUBES AND METHODS OF FORMING SUCH LOW-K DIELECTRIC MATERIALS 有权
标题翻译：基于碳纳米管的低K电介质材料和形成这种低K电介质材料的方法
公开(公告)号：US20060073682A1
公开(公告)日：2006-04-06
申请号：US10711764
申请日：2004-10-04
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/28
CPC分类号： H01L21/02115 , B82Y10/00 , H01L21/02282 , H01L21/3146 , H01L21/3185 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76831 , H01L21/76888 , H01L2221/1047
摘要： A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.
摘要翻译：用于制造半导体器件的低k电介质材料，使用低k电介质材料的半导体结构，以及形成这种介电材料和制造这种结构的方法。低k介电材料包括碳纳米结构，如碳纳米管或碳棒球，其特征在于绝缘电子状态。碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。将碳纳米结构转化为绝缘电子态的一种方法是氟化。

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