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21. 发明申请

US20050226666A1 Printed matter reliability decision method 失效
标题翻译：印刷品可靠性决策方法
公开(公告)号：US20050226666A1
公开(公告)日：2005-10-13
申请号：US10947214
申请日：2004-09-23
申请人： Hirokazu Aoshima , Yoshiyasu Takahashi , Yasuhiro Fujii , Hideo Noyama , Takeshi Matsuki
发明人： Hirokazu Aoshima , Yoshiyasu Takahashi , Yasuhiro Fujii , Hideo Noyama , Takeshi Matsuki
IPC分类号： B41J5/30 , B41M3/14 , B42D15/00 , G03G15/36 , G06T1/00 , G07D7/00 , G07D7/20 , H04N1/387 , H04N1/40 , G06K5/00
CPC分类号： G07D7/20 , B41M3/14 , G07D7/0047
摘要： The problem is to make a reliability decision on printed matter without using special ink or a dedicated blank. At least a part of a feature of a state included in printed matter is recorded by using a predetermined method at the time of printing. At the time of verification, the feature of the state acquired from the printed matter is compared with the feature recorded at the time of printing to conduct verification. As this feature, a feature value determined on the basis of a feature of the state of the printed matter, in the state of the printed matter determined in association with spatial distribution of a coloring portion on the printing surface, at the time when printing first information to be recorded is used.
摘要翻译：问题是在不使用特殊油墨或专用空白的情况下对印刷品进行可靠性决定。通过在打印时使用预定方法来记录包含在打印物中的状态的特征的至少一部分。在验证时，将从印刷品获得的状态的特征与印刷时记录的特征进行比较以进行验证。作为该特征，基于打印物的状态的特征确定的特征值，在与打印表面上的着色部分的空间分布相关联地确定的打印物体的状态下，在打印时使用要记录的信息。

22. 发明授权

US06693360B1 Static type semiconductor memory device 失效
标题翻译：静态型半导体存储器件
公开(公告)号：US06693360B1
公开(公告)日：2004-02-17
申请号：US10383051
申请日：2003-03-07
申请人： Makoto Dei , Yasuhiro Fujii
发明人： Makoto Dei , Yasuhiro Fujii
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L21/76804 , H01L23/485 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact holes provided in the interlayer insulator film and reaching a source and a drain located on either side of the gate electrode, a plug portion formed within each contact hole, and a metal interconnection formed on each plug portion. A space between contact holes located in the interlayer insulator film is made smaller than a space between contact holes on a surface of the interlayer insulator film.
摘要翻译：静电型半导体存储器件的存储单元包括经由绝缘膜形成在半导体衬底的主表面上的MOS晶体管的栅电极，覆盖栅电极的层间绝缘膜，设置在层间绝缘体中的一组接触孔并且到达位于栅电极两侧的源极和漏极，形成在每个接触孔内的插塞部分和形成在每个插塞部分上的金属互连。使位于层间绝缘膜的接触孔之间的间隔比层间绝缘膜的表面的接触孔的间隔小。

23. 发明授权

US06200245B1 Apparatus and method for changing dies 失效
标题翻译：用于更换模具的装置和方法
公开(公告)号：US06200245B1
公开(公告)日：2001-03-13
申请号：US09355198
申请日：1999-07-26
申请人： Yasushi Dodo , Kenichi Ide , Shigeki Narushima , Nobuhiro Tazoe , Yasuhiro Fujii , Sadakazu Masuda , Shuichi Yamashina , Shozo Ikemune
发明人： Yasushi Dodo , Kenichi Ide , Shigeki Narushima , Nobuhiro Tazoe , Yasuhiro Fujii , Sadakazu Masuda , Shuichi Yamashina , Shozo Ikemune
IPC分类号： B23Q3155
CPC分类号： B21J1/04 , B21B15/0042 , B21B2203/36 , Y10S100/918 , Y10T483/10 , Y10T483/1729
摘要： The die changing apparatus for a plate reduction press machine, comprises an upper die support holder 28a and a lower die support holder 28b that are arranged vertically on opposite sides of a transfer line, and support holder guide rails 31 installed on the upper die support holder and extending substantially horizontally in the lateral direction of the transfer line, and an upper die 29a and a lower die 29b are mounted on the upper and lower die support holders, respectively using the rollers onto the dies, fixing devices 30 that fix the upper and lower dies on the upper and lower die support holders, respectively, die fastening members 38 which are placed on each side of the upper and lower dies, opposite each other in such a manner that they can be fastened to both dies, and a die changing mechanism that can move one of the die fastening members in a direction perpendicular to the transfer line.
摘要翻译：用于板材压制机的模具更换装置包括：上模支撑保持器28a和下模支撑保持器28b，其垂直设置在输送线的相对侧;以及支撑托架导轨31，其安装在上模支撑架上并且在传送线的横向方向上基本上水平地延伸，并且上模29a和下模29b分别使用辊安装到上模和下模支撑保持器上，固定装置30固定上和分别设置在上下模具支撑架上的模具，模具紧固构件38，其设置在上模具和下模具的每一侧上，使得它们可以紧固到两个模具，并且模具更换机构，其能够沿垂直于传送线的方向移动模具紧固构件中的一个。

24. 发明授权

US6133781A Semiconductor device utilizing unnecessary electric charge on complementary signal line pair 有权
标题翻译：在互补信号线对上利用不必要的电荷的半导体器件
公开(公告)号：US6133781A
公开(公告)日：2000-10-17
申请号：US349110
申请日：1999-07-08
申请人： Yasuhiro Fujii , Yasurou Matsuzaki
发明人： Yasuhiro Fujii , Yasurou Matsuzaki
IPC分类号： G11C11/401 , G05F3/02 , G11C11/407 , H01L21/8238 , H01L27/092
CPC分类号： G11C11/4097 , G11C11/4094 , G11C7/12 , G11C7/18
摘要： A switch 17 for short-circuiting is connected between the outputs of circuits 15 and 16 each of which outputs a pair of complementary signals .0.S1 and .0.R1. The circuits 15 and 16, and the switch 17 are controlled by a changeover control circuit 18 in response to an input signal .0.A1. To effectively utilizes electric charge which has become unnecessary on a complementary signal line pair, the circuit 18 comprises an edge detecting circuit for providing a pulse to the switch 17 to make it on in response to the edge of the signal .0.A1, and a state control circuit for making the outputs of the circuits 15 and 16 in a high impedance state while the switch 17 being on, and for making the logic states of the signals .0.S1 and .0.R1 completely transit in response to disappearance of the pulse while the switch 17 being off.
摘要翻译：用于短路的开关17连接在各自输出一对互补信号OS1和OR1的电路15和16的输出之间。响应于输入信号OA1，电路15和16以及开关17由转换控制电路18控制。为了有效地利用在互补信号线对上变得不必要的电荷，电路18包括边缘检测电路，用于向开关17提供脉冲以使其响应于信号OA1的边缘而导通，并且状态控制当开关17接通时使电路15和16的输出处于高阻抗状态，并且用于使信号OS1和OR1的逻辑状态响应于开关17断开时的脉冲消失而完全转变的电路。

25. 发明授权

US6108793A Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device 失效
标题翻译：具有时序稳定电路的半导体器件和测试这种半导体器件的方法
公开(公告)号：US6108793A
公开(公告)日：2000-08-22
申请号：US40288
申请日：1998-03-18
申请人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
发明人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
IPC分类号： G01R31/30 , G06F1/04 , H03L7/081 , H03L7/087 , H03L7/095
CPC分类号： H03L7/0805 , G01R31/3016 , G06F1/04 , H03L7/0814 , H03L7/087 , H03L7/095
摘要： A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.
摘要翻译：一种测量定时稳定电路所需的时间的方法，以便对具有第一功能的半导体器件完成定时稳定以复位定时稳定电路，以及第二功能，以输出指示完成的信号公开了定时稳定。该方法包括以下步骤：a）激活定时稳定电路，b）通过使用第二功能来检测定时稳定的定时，以及c）测量定时稳定电路完成定时所需的时间基于时间稳定。

26. 发明授权

US6063640A Semiconductor wafer testing method with probe pin contact 失效
标题翻译：半导体晶圆测试方法与探针接触
公开(公告)号：US6063640A
公开(公告)日：2000-05-16
申请号：US30349
申请日：1998-02-25
申请人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
发明人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
IPC分类号： H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , H01L22/22 , H01L2224/05554 , Y10S438/977
摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.
摘要翻译：半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤来自半导体晶片表面的临时测试膜。临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

27. 发明授权

US5917745A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5917745A
公开(公告)日：1999-06-29
申请号：US40365
申请日：1998-03-18
申请人： Yasuhiro Fujii
发明人： Yasuhiro Fujii
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097 , G11C5/06
CPC分类号： G11C11/4097 , G11C7/18
摘要： A semiconductor memory device according to this invention has a hierarchical bit line structure where a plurality of local bit lines are provided in parallel to each global bit line and some of the local bit lines in the column direction are connected to the global bit line. Such memory device further has an open bit line structure where global bit lines are provided on both sides of sense amplifiers, and has bit-line transfer circuits, provided between the global bit lines and the sense amplifiers, for isolating the global bit lines from the sense amplifiers when the sense amplifiers are activated. The use of the hierarchical bit line structure in combination with the open bit line structure enhances the layout efficiency of memory cells, and the provision of the bit-line transfer circuits overcomes a problem of erroneous data reading which would otherwise be caused by bit line noise inherent to the open bit line structure.
摘要翻译：根据本发明的半导体存储器件具有分层位线结构，其中与每个全局位线并联提供多个局部位线，并且列方向上的一些局部位线连接到全局位线。这种存储器件还具有开放位线结构，其中全局位线设置在读出放大器的两侧，并且具有设置在全局位线和读出放大器之间的位线传输电路，用于将全局位线与读出放大器激活时的读出放大器。结合开放位线结构使用分层位线结构增强了存储器单元的布局效率，并且提供位线传输电路克服了否则将由位线噪声引起的错误数据读取的问题开放位线结构固有的。

28. 发明授权

US5617363A Dynamic random access memory having sense amplifier control circuit supplied with external sense amplifier activating signal 失效
标题翻译：动态随机存取存储器，具有提供有外部读出放大器激活信号的读出放大器控制电路
公开(公告)号：US5617363A
公开(公告)日：1997-04-01
申请号：US517762
申请日：1995-08-22
申请人： Fuminori Yumitori , Yasuhiro Fujii
发明人： Fuminori Yumitori , Yasuhiro Fujii
IPC分类号： G11C11/41 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/4091
摘要： The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.
摘要翻译：本发明涉及一种用于在短时间内有效地发送大量数据的高速数据传输系统。 DRAM至少包括存储单元，读出放大器，/ RAS信号输入，字线（WL）升压信号发生器，读出放大器控制信号发生器和读出放大器驱动信号发生器，其中存储器单元是由多个组构成，读出放大器以对应的多个数字提供，读出放大器控制信号发生器以多个数字提供以对应于多个存储体，并且提供外部读出放大器激活信号端子，其连接到读出放大器控制信号发生器，以独立于/ RAS信号激活读出放大器。

29. 发明授权

US5083132A Planar antenna with active circuit block 失效
标题翻译：具有有源电路块的平面天线
公开(公告)号：US5083132A
公开(公告)日：1992-01-21
申请号：US516549
申请日：1990-04-30
申请人： Minoru Kanda , Mikio Komatsu , Hidetsugu Nunoya , Yasuhiro Fujii , Toshio Abiko
发明人： Minoru Kanda , Mikio Komatsu , Hidetsugu Nunoya , Yasuhiro Fujii , Toshio Abiko
IPC分类号： H01Q21/00 , H01Q23/00
CPC分类号： H01Q23/00 , H01Q21/0087
摘要： A planar antenna has an active circuit block, the whole or part of which is internally mounted to a planar antenna body so that connecting terminal of the block will be connected to a feeding point on power supply plate of the antenna body. Dimensional minimization of the entire antenna can be thereby attained and noise figure of the active circuit can be simultaneously reduced.
摘要翻译：平面天线具有有源电路块，其全部或部分内部安装到平面天线体，使得块的连接端子将连接到天线体的供电板上的馈电点。从而可以实现整个天线的尺寸最小化，并且可以同时降低有源电路的噪声系数。

30. 发明授权

US5011881A Aqueous thermoplastic coating composition for plastics materials and coating method using same 失效
标题翻译：用于塑料材料的水性热塑性涂料组合物和使用其的涂布方法
公开(公告)号：US5011881A
公开(公告)日：1991-04-30
申请号：US465705
申请日：1990-01-16
申请人： Yasuhiro Fujii , Masaru Mitsuji , Junichi Kajima
发明人： Yasuhiro Fujii , Masaru Mitsuji , Junichi Kajima
IPC分类号： B05D7/04 , C08G18/08 , C08J7/04 , C09D175/04
CPC分类号： C08J7/045 , C08G18/0823 , C09D175/04 , B05D2201/00 , B05D7/532 , B05D7/577 , C08J2333/00 , C08J2475/04
摘要： Disclosed are (1) an aqueous thermoplastic coating composition for coating plastics substrates, the composition consisting essentially of:(A) an aqueous acrylic resin and(B) a urethane resin emulsion,the component (B) being a self-emulsifiable urethane emulsion prepared by subjecting a urethane prepolymer to reaction for chain extension by water and emulsification after or during neutralization of the urethane prepolymer with a tertiary amine, the urethane prepolymer consisting essentially of (i) an aliphatic and/or an alicyclic diisocyanate, (ii) a polyether diol and/or polyester diol both having a number-average molecular weight of about 500 to about 5000, (iii) a low-molecular weight polyhydroxyl compound and (iv) a dimethylolalkanoic acid in NCO/OH equivalent ratio of 1.1-1.9 : 1, the amount of the component (A) being about 1 to about 12% by weight and the amount of the component (B) being about 99 to about 88% by weight, based on the combined weight (calculated as solids) of the two components; and (2) a two-coat coating method for coating a plastics substrate, the method comprising the steps of coating a plastics substrate with a base-coat composition containing a coloring pigment and/or metallic pigment, applying a clear coat composition to the cured or uncured coating for forming a transparent coating and curing the clear coating or the two coatings at the same time at a temperature lower than about 120.degree. C., the method being characterized by the use of the aqueous thermoplastic coating composition as defined above in (1) as the base-coat composition.

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