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21. 发明申请

US20110133818A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110133818A1
公开(公告)日：2011-06-09
申请号：US13022611
申请日：2011-02-07
申请人： Tomoko MATSUDAI , Norio Yasuhara , Kazutoshi Nakamura
发明人： Tomoko MATSUDAI , Norio Yasuhara , Kazutoshi Nakamura
IPC分类号： H03K3/01 , H01L29/78
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译：半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

22. 发明申请

US20090065862A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090065862A1
公开(公告)日：2009-03-12
申请号：US12264580
申请日：2008-11-04
申请人： Tomoko MATSUDAI , Norio Yasuhara
发明人： Tomoko MATSUDAI , Norio Yasuhara
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
摘要翻译：一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

23. 发明申请

US20080315305A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080315305A1
公开(公告)日：2008-12-25
申请号：US12141386
申请日：2008-06-18
申请人： Tomoko Matsudai , Norio Yasuhara , Manji Obatake
发明人： Tomoko Matsudai , Norio Yasuhara , Manji Obatake
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/2652 , H01L21/2658 , H01L29/42376 , H01L29/66659 , H01L29/7835
摘要： A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.
摘要翻译：第二导电类型的LDD层位于侧壁绝缘膜下面的半导体层的表面。第二导电类型的源极层在与LDD层相邻的位置处形成在半导体层的表面中。在半导体层的表面上，在与LDD层夹着栅电极的位置处形成第二导电类型的复层。第二导电类型的漏极层在与复层层相邻的位置处形成在半导体层的表面中。再次形成深度为半导体层表面的第一和第二杂质浓度的峰值。第一杂质浓度的峰值小于第二杂质浓度的峰值。

24. 发明申请

US20070034894A1 Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效
标题翻译：包括用作高速开关装置的场效应晶体管和功率器件的半导体装置
公开(公告)号：US20070034894A1
公开(公告)日：2007-02-15
申请号：US11501715
申请日：2006-08-10
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/74
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

25. 发明授权

US5536961A High breakdown voltage semiconductor device 失效
公开(公告)号：US5536961A
公开(公告)日：1996-07-16
申请号：US396794
申请日：1995-03-01
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L29/76
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286
摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

26. 发明授权

US5463231A Method of operating thyristor with insulated gates 失效
公开(公告)号：US5463231A
公开(公告)日：1995-10-31
申请号：US353385
申请日：1994-12-02
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

27. 发明授权

US08212310B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08212310B2
公开(公告)日：2012-07-03
申请号：US13022611
申请日：2011-02-07
申请人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
发明人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译：半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

28. 发明授权

US08110924B2 Semiconductor device and method for manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08110924B2
公开(公告)日：2012-02-07
申请号：US12408390
申请日：2009-03-20
申请人： Kazutoshi Nakamura , Norio Yasuhara , Tomoko Matsudai , Daisuke Minohara
发明人： Kazutoshi Nakamura , Norio Yasuhara , Tomoko Matsudai , Daisuke Minohara
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L23/522 , H01L23/552 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/1132 , H01L2224/1191 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/1411 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.
摘要翻译：在DC-DC转换器中，在硅衬底上设置多层布线层，并且在硅衬底和多层布线层中形成控制输入电路和输出电路的控制电路。此外，设置覆盖多层布线层的密封树脂层和连接到多层布线层的最上布线的连接构件，其穿透密封树脂层并具有从密封树脂层的上表面突出的上端部。连接构件的上端部由突出电极形成。与输出电路的端子连接的连接构件的水平横截面面积大于与控制电路的端子连接的连接构件的水平截面积。

29. 发明授权

US08067801B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08067801B2
公开(公告)日：2011-11-29
申请号：US12181692
申请日：2008-07-29
申请人： Tomoko Matsudai , Norio Yasuhara , Manji Obatake
发明人： Tomoko Matsudai , Norio Yasuhara , Manji Obatake
IPC分类号： H01L29/735
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L27/088 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.
摘要翻译：提供了一种半导体器件，其包括形成在半导体层中的第一晶体管和第二晶体管。第一晶体管包括第一源极区域和与第一源极区域夹持第一栅电极的第一漏极区域。第二晶体管包括LDD区和漂移区，其夹持具有LDD区的第二栅极，以及与漂移区相邻的第二漏极区，以将第二栅电极夹在第二源极区。第一栅电极具有形成在其侧面上的第一侧壁，并且第二栅电极具有形成在其侧面上的第二侧壁。沿着第一绝缘体的前者的宽度与第二绝缘体的宽度不同。

30. 发明授权

US07906808B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07906808B2
公开(公告)日：2011-03-15
申请号：US12476147
申请日：2009-06-01
申请人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
发明人： Tomoko Matsudai , Norio Yasuhara , Kazutoshi Nakamura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译：半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

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