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21. 发明申请

US20060145792A1 STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH 有权
标题翻译：铰链类型MEMS开关的结构和方法
公开(公告)号：US20060145792A1
公开(公告)日：2006-07-06
申请号：US10905449
申请日：2005-01-05
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要翻译：描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

22. 发明申请

US20060087400A1 Thin Film Resistors of Different Materials 失效
标题翻译：不同材料的薄膜电阻器
公开(公告)号：US20060087400A1
公开(公告)日：2006-04-27
申请号：US10711460
申请日：2004-09-20
申请人： Anil Chinthakindi , Anita Madan , Kenneth Stein , Kwong Wong
发明人： Anil Chinthakindi , Anita Madan , Kenneth Stein , Kwong Wong
IPC分类号： H01C1/012
CPC分类号： H01C17/075 , H01C7/006 , H01C7/06
摘要： An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.
摘要翻译：集成电路包括双层薄膜电阻器，其中下层是控制上层晶体结构的晶种层。可以选择下层的厚度和上层的厚度以形成具有设计值的TCR的电阻器。

23. 发明申请

US20050282341A1 High-temperature stable gate structure with metallic electrode 有权
标题翻译：具有金属电极的高温稳定栅极结构
公开(公告)号：US20050282341A1
公开(公告)日：2005-12-22
申请号：US10869658
申请日：2004-06-16
申请人： Dae-Gyu Park , Oleg Gluschenkov , Michael Gribelyuk , Kwong Wong
发明人： Dae-Gyu Park , Oleg Gluschenkov , Michael Gribelyuk , Kwong Wong
IPC分类号： H01L21/28 , H01L21/336 , H01L21/44 , H01L29/49 , H01L29/51
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.
摘要翻译：本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

24. 发明申请

US20050200024A1 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US20050200024A1
公开(公告)日：2005-09-15
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
发明人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

25. 发明申请

US20050067745A1 Method and apparatus for deposition & formation of metal silicides 审中-公开
标题翻译：用于沉积和形成金属硅化物的方法和装置
公开(公告)号：US20050067745A1
公开(公告)日：2005-03-31
申请号：US10674302
申请日：2003-09-30
申请人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
发明人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
IPC分类号： C22F1/00 , C23C14/16 , C23C14/58
CPC分类号： C23C14/5806 , C23C14/16
摘要： Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.
摘要翻译：公开了一种在硅材料上形成硅化物的方法和结构。本发明将硅材料置于真空环境中，在硅材料上形成金属，然后在不破坏真空环境的情况下加热硅表面和金属。当金属沉积时，形成金属和加热硅的工艺可以同时进行而不破坏真空环境以形成硅化物。在上述处理之后，本发明可以从真空环境中去除硅表面，并对硅表面进行附加加热。第一加热工艺形成一硅化物，另外的加热形成二硅化物。

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