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21. 发明授权

US07724079B1 Programmable logic enabled dynamic offset cancellation 有权
标题翻译：可编程逻辑使能动态偏移消除
公开(公告)号：US07724079B1
公开(公告)日：2010-05-25
申请号：US11954925
申请日：2007-12-12
申请人： Sergey Yuryevich Shumarayev
发明人： Sergey Yuryevich Shumarayev
IPC分类号： H03F1/02 , H04B1/04
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/4521 , H03F3/45748 , H03F3/45973 , H03F2203/45136 , H03F2203/45212 , H03F2203/45236 , H03F2203/45366 , H03F2203/45482 , H03F2203/45494 , H03F2203/45681 , H03F2203/45702
摘要： Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.
摘要翻译：提供技术和电路用于以编程方式控制集成电路中的信号偏移。在一个实施例中，具有偏移消除电路的缓冲器电路接收信号并将该信号发送到可编程逻辑电路。可编程逻辑使用可编程资源和/或一个或多个算法来测量与偏移相关联的集成电路操作和/或操作错误。控制信号被反馈到偏移消除电路的输入端。在一个实施例中，偏移消除电路响应于所接收的偏移消除信号的大小来调整信号的偏移，直到与偏移相关联的变化和/或操作误差的大小不再归因于偏移。

22. 发明授权

US08081706B2 Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry 有权
标题翻译：多通道，高速，收发器电路中的车道对车道偏斜减少
公开(公告)号：US08081706B2
公开(公告)日：2011-12-20
申请号：US11211989
申请日：2005-08-24
申请人： Sergey Yuryevich Shumarayev
发明人： Sergey Yuryevich Shumarayev
IPC分类号： H04L27/00
CPC分类号： H04L25/14
摘要： Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to changes in data rate detected by the CDR circuitry.
摘要翻译：可控延迟电路包括在多通道，高速，串行发射器和/或接收器电路的每个通道中，以补偿或至少帮助补偿各个通道之间的可能的偏斜（不同的信号传播时间）。在采用CDR电路的系统中，延迟电路可以由从CDR电路导出的信号至少部分地控制，以使由延迟电路影响的延迟量至少部分地响应由CDR电路检测到的数据速率的变化。

23. 发明申请

US20110068845A1 SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 有权
标题翻译：用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路
公开(公告)号：US20110068845A1
公开(公告)日：2011-03-24
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： G06F1/04 , H03K3/01
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

24. 发明授权

US07702011B2 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US07702011B2
公开(公告)日：2010-04-20
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

25. 发明授权

US07324031B1 Dynamic bias circuit 有权
标题翻译：动态偏置电路
公开(公告)号：US07324031B1
公开(公告)日：2008-01-29
申请号：US11355678
申请日：2006-02-15
申请人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
发明人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
IPC分类号： H03M1/66
CPC分类号： G11C7/12 , G11C7/1045 , H03M1/662
摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.
摘要翻译：偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。通过时域复用方案，D2A可由均衡电路的控制旋钮共享。偏置电路包括还耦合到主寄存器框架的解码器。还包括一个输出使能逻辑模块。当数据链中的数据根据时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。还提供了一种通过偏置电路调整信号的方法。

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