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21. 发明授权

US06310805B1 Architecture for a dual-bank page mode memory with redundancy 有权
标题翻译：具有冗余的双存储页面模式存储器的架构
公开(公告)号：US06310805B1
公开(公告)日：2001-10-30
申请号：US09676902
申请日：2000-10-02
申请人： Yasushi Kasa , Ming-Huei Shing
发明人： Yasushi Kasa , Ming-Huei Shing
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/702 , G11C2216/22
摘要： A memory circuit (100) includes address circuitry (104) configured to receive address data and a plurality of I/O buffers (112). A core cell array (102) includes core cells and redundant core cells. Sense amplifiers (108) including read sense amplifiers (132) and redundant sense amplifiers may be coupled to the I/O buffers by word selection circuitry (110). Redundancy is implemented on an I/O-by-I/O basis, so that a redundant core cell and sense amplifier may be substituted for any failed bit in the core cell array.
摘要翻译：存储器电路（100）包括被配置为接收地址数据的地址电路（104）和多个I / O缓冲器（112）。核心单元阵列（102）包括核心单元和冗余核心单元。包括读出放大器（132）和冗余读出放大器的检测放大器（108）可以由字选择电路（110）耦合到I / O缓冲器。冗余以I / O / I / O为基础实现，使得冗余核心单元和读出放大器可以替代核心单元阵列中的任何故障位。

22. 发明授权

US06208564B1 High voltage comparator 有权
标题翻译：高电压比较器
公开(公告)号：US06208564B1
公开(公告)日：2001-03-27
申请号：US09429987
申请日：1999-10-29
申请人： Shigekazu Yamada , Yasushi Kasa
发明人： Shigekazu Yamada , Yasushi Kasa
IPC分类号： G11C700
CPC分类号： G11C16/08 , G11C5/143 , G11C16/30 , G11C16/32
摘要： A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.
摘要翻译：高电压比较器电路快速识别程序操作所需的预定电压的电压电平。通过一系列晶体管，确定了预定电压何时处于其工作电压电平的精确定时。

23. 发明授权

US6163478A Common flash interface implementation for a simultaneous operation flash memory device 有权
标题翻译：通用闪存接口实现用于同时操作闪存设备
公开(公告)号：US6163478A
公开(公告)日：2000-12-19
申请号：US421774
申请日：1999-10-19
申请人： Yasushi Kasa , Fan W. Lai
发明人： Yasushi Kasa , Fan W. Lai
IPC分类号： G11C16/20 , G11C17/12 , G11C16/04
CPC分类号： G11C17/123 , G11C16/20 , G11C2216/22
摘要： An alterable Common Flash Interface ("CFI") is disclosed which includes a storage array which stores the CFI data. The storage array provides sub-circuits for encoding the CFI data. The sub-circuits comprise elements which can be altered by changing a single metal layer of the fabrication process.
摘要翻译：公开了一种可变通用闪存接口（“CFI”），其包括存储CFI数据的存储阵列。存储阵列提供用于编码CFI数据的子电路。子电路包括可以通过改变制造工艺的单个金属层来改变的元件。

24. 发明授权

US5590074A Nonvolatile semiconductor memory 失效
公开(公告)号：US5590074A
公开(公告)日：1996-12-31
申请号：US466732
申请日：1995-06-06
申请人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
发明人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
IPC分类号： G11C16/26 , G11C16/30 , G11C29/04 , G11C11/34
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

25. 发明申请

US20070052064A1 Semiconductor device and programming method therefor 有权
标题翻译：半导体器件及其编程方法
公开(公告)号：US20070052064A1
公开(公告)日：2007-03-08
申请号：US11414081
申请日：2006-04-27
申请人： Yasushi Kasa
发明人： Yasushi Kasa
IPC分类号： H01L29/00
CPC分类号： H01L27/101
摘要： A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the basis of programming information, and a read circuit (40) reading the programming information by determining whether such an opening (21) is formed in the program layer (20) by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer (20) may be made of a material having a dielectric constant higher than that of air or the program layer (20) may be made of a conductor or a material having a dielectric constant lower than that of air. Thus, trimming information or information on a device identification (ID) can be stored, even if the semiconductor device is a logic device that does not have a memory transistor, by detecting the information that is determined by the electrostatic capacitance that varies depending on whether or not there is provided an opening (21).
摘要翻译：提供一种半导体器件，其包括设置在半导体衬底（10）上方的一对金属互连（B，C），设置在该对金属互连（B，C）上的编程层（20），并且其中开口 21）可以基于编程信息在编程层（20）中选择性地形成;以及读取电路（40），通过确定在程序层（20）中是否形成这样的开口（21）来读取编程信息利用一对金属互连（B，C）之间的静电电容。编程层（20）可以由具有高于空气介电常数的介电常数的材料制成，或者编程层（20）可以由具有低于空气介电常数的介电常数的导体或材料制成。因此，即使半导体器件是不具有存储晶体管的逻辑器件，也可以通过检测由静电电容确定的信息根据是否取决于是否变化的信息来存储关于器件识别（ID）的修整信息或信息或者不设置开口（21）。

26. 发明授权

US06618288B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06618288B2
公开(公告)日：2003-09-09
申请号：US10265106
申请日：2002-10-07
申请人： Takao Akaogi , Yasushi Kasa
发明人： Takao Akaogi , Yasushi Kasa
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

27. 发明授权

US06563738B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06563738B2
公开(公告)日：2003-05-13
申请号：US10150017
申请日：2002-05-20
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

28. 发明授权

US06397313B1 Redundant dual bank architecture for a simultaneous operation flash memory 有权
标题翻译：冗余双行架构，用于同时运行闪存
公开(公告)号：US06397313B1
公开(公告)日：2002-05-28
申请号：US09632390
申请日：2000-08-04
申请人： Yasushi Kasa , Guowei Wang
发明人： Yasushi Kasa , Guowei Wang
IPC分类号： G06F1206
CPC分类号： G11C29/781 , G11C2216/22
摘要： The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks that can be configured to be located in an upper bank or a sliding lower bank. The redundant blocks are comprised of sectors and each sector contains columns of memory cells. During simultaneous operation, the memory device is capable of reading the columns of memory cells in one bank and writing columns of memory cells in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells that are defective in one bank by electrically exchanging them with redundant columns of memory cells and, at the same time, repair columns of memory cells that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits that are configurably associated with the redundant blocks based on the bank location of the redundant blocks. The address CAM circuits are configured by a redundancy CAM read drain decoder circuit.
摘要翻译：本发明公开了基于扇区的冗余，其能够在同时操作期间使用双组存储器设备中的多个冗余列的存储单元进行修复。同时操作存储装置包括多个冗余块，其可被配置为位于上层或滑动下层。冗余块由扇区组成，每个扇区包含存储单元列。在同步操作期间，存储器件能够读取一个存储体中的存储单元的列，并且同时在另一个存储体中写入存储单元的列。此外，同时操作存储器件使用基于扇区的冗余来通过与存储器单元的冗余列电交换来修复存储单元中有缺陷的存储器单元的列，并且同时修复有缺陷的存储器单元的列在另一家银行。基于双银行扇区的冗余包括多个地址CAM电路，其基于冗余块的存储单元位置与冗余块可配置地相关联。地址CAM电路由冗余CAM读取漏极解码器电路配置。

29. 发明授权

US5608670A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5608670A
公开(公告)日：1997-03-04
申请号：US436721
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
摘要翻译：本发明涉及擦除闪存的改进。本发明的目的是缩短擦除时间。在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

30. 发明授权

US5592427A Semiconductor memory having a sense amplifier with load transistors having different load characteristics 失效
标题翻译：半导体存储器具有具有不同负载特性的负载晶体管的读出放大器
公开(公告)号：US5592427A
公开(公告)日：1997-01-07
申请号：US463636
申请日：1995-06-06
申请人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
发明人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
IPC分类号： G01R31/28 , G11C5/14 , G11C7/06 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C29/021 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C2029/5006
摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.
摘要翻译：本发明的目的是提供一种能够容易且有效地进行测试的半导体器件。非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及状态寄存器2，用于在电路9的操作完成时存储存储器的操作状态，其中在存储单元矩阵17的地址之外提供两种虚拟单元D1，D2，D3。。。，其值固定为从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

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