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21. 发明申请

US20070099361A1 Method for forming a semiconductor structure and structure thereof 有权
公开(公告)号：US20070099361A1
公开(公告)日：2007-05-03
申请号：US11263119
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

22. 发明申请

US20070099353A1 Method for forming a semiconductor structure and structure thereof 有权
标题翻译：半导体结构的形成方法及其结构
公开(公告)号：US20070099353A1
公开(公告)日：2007-05-03
申请号：US11263120
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785 , Y10S438/938
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层上的应变半导体层的衬底，提供用于形成具有第一导电类型的第一多个器件的第一器件区域，提供第二器件区域，用于形成具有第第二导电类型，并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的第一器件区域中的应变半导体层的应变。或者，形成半导体结构包括提供具有第一导电类型的第一区域，形成覆盖第一区域的至少有源区域的绝缘层，各向异性地蚀刻绝缘层，以及在各向异性蚀刻绝缘层之后，覆盖绝缘层的至少一部分的材料。

23. 发明申请

US20060228842A1 Transistor fabrication using double etch/refill process 有权
标题翻译：使用双重蚀刻/补充工艺的晶体管制造
公开(公告)号：US20060228842A1
公开(公告)日：2006-10-12
申请号：US11101354
申请日：2005-04-07
申请人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
发明人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
IPC分类号： H01L21/338 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。第一间隔物（124）形成在栅电极（120）的侧壁上。使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。第一s / d沟槽（130）填充有第一s / d结构（132）。第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。第二s / d沟槽（150）填充有第二s / d结构（152）。填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

24. 发明申请

US20070238233A1 Method of making a multiple crystal orientation semiconductor device 有权
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：US20070238233A1
公开(公告)日：2007-10-11
申请号：US11393563
申请日：2006-03-30
申请人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
IPC分类号： H01L21/337
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种类型的晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

25. 发明申请

US20070048919A1 Modified hybrid orientation technology 失效
标题翻译：改进的混合取向技术
公开(公告)号：US20070048919A1
公开(公告)日：2007-03-01
申请号：US11209869
申请日：2005-08-23
申请人： Olubunmi Adetutu , Mariam Sadaka , Ted White , Bich-Yen Nguyen
发明人： Olubunmi Adetutu , Mariam Sadaka , Ted White , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161）电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。

26. 发明授权

US07781277B2 Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit 有权
标题翻译：应变绝缘子集成电路中布局优化的选择性单轴应力松弛
公开(公告)号：US07781277B2
公开(公告)日：2010-08-24
申请号：US11383113
申请日：2006-05-12
申请人： Bich-Yen Nguyen , Voon-Yew Thean
发明人： Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0207 , H01L29/1033 , H01L29/41758 , H01L29/41775 , H01L29/6659 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.
摘要翻译：集成电路包括NMOS和PMOS晶体管。 NMOS具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS具有沿第一和第二轴具有第三和第四应力值的应变通道。第一值应力与第三值不同，第二值与第四值不同。 NMOS和PMOS具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS的SA可以小于NMOS的SA。集成电路可以包括氮化硅在NMOS上的拉伸应力源和在PMOS上的氮化硅的压应力。

27. 发明授权

US07265004B2 Electronic devices including a semiconductor layer and a process for forming the same 有权
标题翻译：包括半导体层的电子器件及其形成方法
公开(公告)号：US07265004B2
公开(公告)日：2007-09-04
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

28. 发明授权

US07230264B2 Semiconductor transistor having structural elements of differing materials 有权
标题翻译：具有不同材料结构元件的半导体晶体管
公开(公告)号：US07230264B2
公开(公告)日：2007-06-12
申请号：US11247866
申请日：2005-10-07
申请人： Voon-Yew Thean , Dina H. Triyoso , Bich-Yen Nguyen
发明人： Voon-Yew Thean , Dina H. Triyoso , Bich-Yen Nguyen
IPC分类号： H01L29/06
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.
摘要翻译：使用半导体衬底形成晶体管，并形成覆盖半导体衬底的控制电极。第一电流电极形成在半导体衬底内并与控制电极相邻。第一电流电极具有第一预定半导体材料。第二电流电极形成在半导体衬底内并与控制电极相邻，以在半导体衬底内形成通道。第二电流电极具有与第一预定半导体材料不同的第二预定半导体材料。选择第一预定半导体材料以优化第一电流电极的带隙能量，并且选择第二预定半导体材料以优化通道的应变。

29. 发明授权

US07226833B2 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US07226833B2
公开(公告)日：2007-06-05
申请号：US10977423
申请日：2004-10-29
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

30. 发明授权

US07226820B2 Transistor fabrication using double etch/refill process 有权
标题翻译：使用双重蚀刻/补充工艺的晶体管制造
公开(公告)号：US07226820B2
公开(公告)日：2007-06-05
申请号：US11101354
申请日：2005-04-07
申请人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。第一间隔物（124）形成在栅电极（120）的侧壁上。使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。第一s / d沟槽（130）填充有第一s / d结构（132）。第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。第二s / d沟槽（150）填充有第二s / d结构（152）。填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

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