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    • 21. 发明申请
    • CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD
    • 时钟数据恢复电路和时钟数据恢复方法
    • US20120170692A1
    • 2012-07-05
    • US13394801
    • 2010-09-07
    • Kazuhisa SunagaKouichi Yamaguchi
    • Kazuhisa SunagaKouichi Yamaguchi
    • H04L27/22
    • H04L7/0334H04L7/0025H04L27/38
    • A clock data recovery circuit includes: a demodulation filter that receives a transmission signal transmitted by two orthogonal carrier waves having I and Q phases and executes demodulation to obtain a demodulated wave having an phase and a demodulated wave having a Q phase from the transmission signal; a first determination circuit that determines whether an absolute value of one of the two demodulated waves is greater than an eye opening maximum value at an ideal clock phase of the transmission signal; a second determination circuit that determines whether the one demodulated wave is greater than zero; a third determination circuit that determines whether the other one of the two demodulated waves is greater than zero; and a phase comparison unit that detects whether a phase of a clock signal included in the transmission signal is leading a phase of a data signal included in the transmission signal, based on determination results obtained by the first to third determination circuits.
    • 时钟数据恢复电路包括:解调滤波器,其接收由具有I相和Q相的两个正交载波发送的发送信号,并执行解调以从发送信号中获得具有Q相的相位和解调波的解调波; 第一确定电路,确定两个解调波中的一个的绝对值是否大于在发送信号的理想时钟相位处的开眼最大值; 确定所述一个解调波是否大于零的第二确定电路; 确定所述两个解调波中的另一个是否大于零的第三确定电路; 以及相位比较单元,其基于由所述第一至第三判定电路获得的判定结果,检测所述发送信号中包含的时钟信号的相位是否在包含在所述发送信号中的数据信号的相位。