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21. 发明申请

US20130329621A1 TERMINAL DEVICE, WIRELESS BASE STATION WIRELESSLY COMMUNICATING WITH THE SAME, AND WIRELESS COMMUNICATION SYSTEM USING TERMINAL DEVICE AND WIRELESS BASE STATION 有权
标题翻译：终端设备，无线基站与无线基站，以及使用终端设备和无线基站的无线通信系统
公开(公告)号：US20130329621A1
公开(公告)日：2013-12-12
申请号：US14001060
申请日：2012-02-16
申请人： Yoshihisa Kondo , Hiroyuki Yomo , Suhua Tang , Sadao Obana , Tetsuya Ito , Koichi Yoshimura , Masahito Iwai , Toshiyasu Tanaka , Hiroyuki Iizuka
发明人： Yoshihisa Kondo , Hiroyuki Yomo , Suhua Tang , Sadao Obana , Tetsuya Ito , Koichi Yoshimura , Masahito Iwai , Toshiyasu Tanaka , Hiroyuki Iizuka
IPC分类号： H04W52/02
CPC分类号： H04W52/0225 , H04W52/0206 , H04W52/0229 , Y02D70/00 , Y02D70/142 , Y02D70/144
摘要： A terminal device 2 transmits a wireless frame having a frame length or amplitude that represents the ID of a wireless base station 1 to be woken up to the wireless base station 1. The wireless base station 1 detects the wakeup ID from the frame length or amplitude of the wireless frame from the terminal device 2, and, if the detected wakeup ID is identical with its own ID, transitions from a sleep mode to an operating mode. In this case, the wireless frame is the same wireless frame as that transmitted and received by the wireless communication module of the terminal device 2 to and from the wireless base station 1.
摘要翻译：终端装置2将具有表示要唤醒的无线基站1的ID的帧长度或幅度的无线帧发送到无线基站1.无线基站1从帧长度或振幅检测唤醒ID 的终端设备2的无线帧，并且如果检测到的唤醒ID与其自身的ID相同，则从休眠模式转换到操作模式。在这种情况下，无线帧与终端装置2的无线通信模块向无线基站1发送和接收的无线帧相同。

22. 发明授权

US08572465B2 Nonvolatile semiconductor memory system having first and second error correction units 有权
标题翻译：具有第一和第二误差校正单元的非易失性半导体存储器系统
公开(公告)号：US08572465B2
公开(公告)日：2013-10-29
申请号：US12848476
申请日：2010-08-02
申请人： Hironori Uchikawa , Yoshihisa Kondo
发明人： Hironori Uchikawa , Yoshihisa Kondo
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , H03M13/05 , Y02D10/13
摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
摘要翻译：非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。半导体存储器存储用LDPC码编码的数据帧。所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

23. 发明申请

US20120297273A1 MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD 有权
标题翻译：存储器控制器，半导体存储器和解码方法
公开(公告)号：US20120297273A1
公开(公告)日：2012-11-22
申请号：US13235395
申请日：2011-09-18
申请人： Kenji SAKAUE , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
发明人： Kenji SAKAUE , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/00 , H03M13/1105 , H03M13/1111 , H03M13/1137 , H03M13/116 , H03M13/1177 , H03M13/1185 , H03M13/1188 , H03M13/45 , H03M13/6502 , H03M13/6505 , H03M13/6577
摘要： A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.
摘要翻译：一种存储器控制器，包括：缓冲器，被配置为基于由单位矩阵的块和多个块组成的校验矩阵，通过部分并行处理来执行由LDPC解码器解码的帧单元数据，其中，每行单位矩阵顺序地移位并存储从存储器部分读取的数据的阈值判定信息，被配置为将阈值判定信息转换为LLR的LLR转换部分，被配置为存储概率信息＆lt; bgr的LMEM; 在迭代处理期间计算的重复执行列处理和基于等于或小于块的大小的迭代单元中的LLR的行处理以及被配置为传送概率信息＆bgr的CPU核心; 每次迭代单元中的迭代处理完成时，将LMEM存储在缓冲区中。

24. 发明授权

US08184584B2 Wireless device which selects routes excluding loop routes and a mesh network including the same 有权
标题翻译：选择不包括循环路由的路由的无线设备和包括该路由的网状网络
公开(公告)号：US08184584B2
公开(公告)日：2012-05-22
申请号：US12256753
申请日：2008-10-23
申请人： Yoshihisa Kondo , Satoko Itaya , Peter Davis , Ryutaro Suzuki , Sadao Obana , Tetsuya Ito , Akira Matsumoto
发明人： Yoshihisa Kondo , Satoko Itaya , Peter Davis , Ryutaro Suzuki , Sadao Obana , Tetsuya Ito , Akira Matsumoto
IPC分类号： H04W4/00
CPC分类号： H04W40/16 , H04L45/125 , H04L45/18
摘要： In wireless communication using links with neighbor wireless devices, a wireless device calculates ratios of throughput to maximum throughput for the links and calculates the costs of the links using the calculated ratios. Then the wireless device finds, for each destination, a route in which the sum of such calculated link costs is the minimum, and sends a packet to the destination using the route. As a consequence, routing can be done according to an isotonic, easy-to-implement routing protocol.
摘要翻译：在使用与相邻无线设备的链路的无线通信中，无线设备计算链路的吞吐量与最大吞吐量的比率，并使用所计算的比率来计算链路的成本。然后，无线设备针对每个目的地找到这样计算的链路成本的总和最小的路由，并且使用该路由向目的地发送分组。因此，可以根据等渗，易于实现的路由协议完成路由。

25. 发明授权

US08036034B2 Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data 失效
标题翻译：配备有用于读取数据的读出放大器和阈值电压信息数据的半导体存储装置
公开(公告)号：US08036034B2
公开(公告)日：2011-10-11
申请号：US12564425
申请日：2009-09-22
申请人： Hitoshi Shiga , Yoshihisa Kondo
发明人： Hitoshi Shiga , Yoshihisa Kondo
IPC分类号： G11C16/26
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C29/00
摘要： A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.
摘要翻译：半导体存储装置包括：读出放大器电路; 第一数据保持电路和第二数据保持电路，被配置为保持数据和阈值电压信息，第二数据保持电路将数据和阈值电压信息输出到外部; 以及控制电路，被配置为控制操作。感测放大器电路被配置为同时执行数据读取操作和阈值电压信息读取操作。控制电路被配置为控制读取操作，使得先前完成读取操作的数据或阈值电压信息中的任何一个从第二数据保持电路输出，另一个数据或阈值电压信息读取操作尚未完成，从存储单元阵列中读出并保留在第一数据保持电路中。

26. 发明申请

US20110219284A1 NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：非易失性半导体存储器系统
公开(公告)号：US20110219284A1
公开(公告)日：2011-09-08
申请号：US12848476
申请日：2010-08-02
申请人： Hironori Uchikawa , Yoshihisa Kondo
发明人： Hironori Uchikawa , Yoshihisa Kondo
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10 , H03M13/05 , Y02D10/13
摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
摘要翻译：非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。半导体存储器存储用LDPC码编码的数据帧。所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

27. 发明申请

US20080192724A1 Wireless device which can improve stability in wireless communications and wireless network using the same 有权
标题翻译：无线设备可以提高无线通信和使用其的无线网络的稳定性
公开(公告)号：US20080192724A1
公开(公告)日：2008-08-14
申请号：US12068913
申请日：2008-02-13
申请人： Yoshihisa Kondo , Tetsuya Ito , Akira Matsumoto , Jun Hasegawa , Satoko Itaya , Kenichi Abe , Peter Davis , Naoto Kadowaki , Sadao Obana
发明人： Yoshihisa Kondo , Tetsuya Ito , Akira Matsumoto , Jun Hasegawa , Satoko Itaya , Kenichi Abe , Peter Davis , Naoto Kadowaki , Sadao Obana
IPC分类号： H04J3/00
CPC分类号： H04W28/22 , H04L47/10 , H04L47/14 , H04L47/25 , H04W84/18
摘要： When wireless communications are made between a first wireless device and a second wireless device along a route, two wireless devices which exist between the first and second wireless devices each determine the lowest maximum transmission rate (11 Mbps) in the wireless intervals on the route from themselves to the second wireless device to be their own transmission rate txRate (11 Mbps) and two other wireless devices which exist between the first and second wireless devices each determine the lowest maximum transmission rate (54 Mbps) in the wireless intervals on the route from themselves to the second wireless device to be their own transmission rate txRate (54 Mbps).
摘要翻译：当沿着路线在第一无线设备和第二无线设备之间进行无线通信时，存在于第一和第二无线设备之间的两个无线设备各自确定在路由上的无线间隔中的最低最大传输速率（11Mbps）它们自己到第二无线设备成为它们自己的传输速率txRate（11Mbps）和存在于第一和第二无线设备之间的另外两个无线设备，每个无线设备确定在路由上的无线间隔中的最低最大传输速率（54Mbps）自己将第二个无线设备作为自己的传输速率txRate（54 Mbps）。

28. 发明授权

US5206826A Floating-point division cell 失效
标题翻译：浮点分割单元格
公开(公告)号：US5206826A
公开(公告)日：1993-04-27
申请号：US787926
申请日：1991-11-06
申请人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
发明人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
IPC分类号： G06F7/537 , G06F7/483 , G06F7/506 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/382 , G06F2207/5352 , G06F7/4873
摘要： A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.
摘要翻译：由部分余数数据寄存器组成的浮点分割单元，用于存储并行余数数据或第三部分余数数据，用于存储并行除数数据或第三除数数据的除数数据寄存器，用于接收低电平的低位除数数据发生器除数数据的低阶部分和低阶除数数据，低阶部分余数计算器，用于通过将低阶除数数据和2的倍数相乘并计算新的低阶数来获得低阶多因子数据通过从部分余数数据的低位部分中减去或添加低阶多因子数据的部分余数数据，高阶除数数据发生器，用于接收除数数据的高阶部分，高阶除数数据和高阶部分余数计算器，用于通过将高阶除数数据和2的倍数相乘在一起来获得高阶多因子数据，并计算新的高除数数据通过从/部分余数数据的高阶部分中减去或添加高阶多因数数据，来获得h阶部分余数数据。

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