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21. 发明申请

US20110084278A1 THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110084278A1
公开(公告)日：2011-04-14
申请号：US12576591
申请日：2009-10-09
申请人： Yong-Soo Cho , Kyo-Ho Moon , Hoon Choi
发明人： Yong-Soo Cho , Kyo-Ho Moon , Hoon Choi
IPC分类号： H01L33/00 , H01L21/336
CPC分类号： H01L29/4908 , H01L27/1214 , H01L29/78648
摘要： The present invention relates to a thin-film transistor in a liquid crystal display device and a method of fabricating the same, and the thin-film transistor may be configured by including a first gate electrode formed on an insulating substrate; a first gate insulation film formed on the insulating substrate including the first gate electrode; an active layer formed on the first gate insulation film; source/drain electrodes formed on the active layer and arranged at both sides of the first gate electrode; a second gate insulation film formed on the active layer and the first gate insulation film including the source/drain electrodes and provided with a contact hole for exposing part of the drain electrode; a second gate electrode overlapped with the first gate electrode on the second gate insulation film; and a pixel electrode electrically connected to the drain electrode through the contact hole.
摘要翻译：液晶显示装置中的薄膜晶体管及其制造方法技术领域本发明涉及液晶显示装置中的薄膜晶体管及其制造方法，薄膜晶体管可以通过包括形成在绝缘基板上的第一栅电极构成，形成在包括所述第一栅极的所述绝缘基板上的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的有源层; 源极/漏电极，形成在有源层上，并布置在第一栅电极的两侧; 形成在所述有源层上的第二栅极绝缘膜和包括所述源极/漏极的所述第一栅极绝缘膜，并且设置有用于使所述漏极的一部分露出的接触孔; 在所述第二栅极绝缘膜上与所述第一栅电极重叠的第二栅电极; 以及通过接触孔与漏电极电连接的像素电极。

22. 发明申请

US20110018600A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20110018600A1
公开(公告)日：2011-01-27
申请号：US12897208
申请日：2010-10-04
申请人： Jin-Il CHUNG , Hoon Choi
发明人： Jin-Il CHUNG , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

23. 发明授权

US07859316B2 Delay locked loop and operating method thereof 有权
标题翻译：延迟锁定环及其操作方法
公开(公告)号：US07859316B2
公开(公告)日：2010-12-28
申请号：US12829938
申请日：2010-07-02
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/087
摘要： A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.
摘要翻译：延迟锁定环（DLL）包括延迟锁定单元，其被配置为产生对应于参考时钟的第一和第二时钟沿的第一和第二延迟时钟，以实现延迟锁定; 相位检测单元，被配置为检测第一和第二延迟时钟之间的相位差，以输出权重选择信号; 权重存储单元，被配置为存储从所述第一和第二延迟时钟被延迟锁定的时间点起的预定时段期间获得的加权选择信号; 以及相位混合单元，被配置为混合第一和第二延迟时钟的相位，以通过将与存储的权重选择信号相对应的权重施加在权重存储单元中来输出DLL时钟。

24. 发明授权

US07843745B2 Delay locked operation in semiconductor memory device 有权
标题翻译：在半导体存储器件中延迟锁定操作
公开(公告)号：US07843745B2
公开(公告)日：2010-11-30
申请号：US12181761
申请日：2008-07-29
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.
摘要翻译：半导体存储器件具有能够适当地控制各种操作模式中的延迟锁定环路的控制电路。半导体存储器件包括用于外部接收系统时钟以将其作为内部时钟输出的时钟缓冲器，用于控制内部时钟的延迟以使得数据输出定时与系统时钟同步的延迟锁定环单元; 数据输出缓冲器，用于使数据与延迟锁定的内部时钟同步，从而输出数据;以及时钟缓冲器控制单元，响应于先前的操作状态，用于产生控制时钟缓冲器的接通/断开切换的使能信号。

25. 发明授权

US07830187B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07830187B2
公开(公告)日：2010-11-09
申请号：US12327745
申请日：2008-12-03
申请人： Jin-Il Chung , Hoon Choi
发明人： Jin-Il Chung , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

26. 发明申请

US20090292420A1 METHOD OF REDUCING CURRENT CONSUMPTION OF ELECTRIC HYDRAULIC POWER STEERING SYSTEM FOR VEHICLE 有权
标题翻译：降低电动液压动力转向系统电流消耗的方法
公开(公告)号：US20090292420A1
公开(公告)日：2009-11-26
申请号：US12331967
申请日：2008-12-10
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： B62D6/00
CPC分类号： B62D5/065
摘要： A method of reducing current consumption of an electric hydraulic power steering system for a vehicle includes determining whether or not a steering wheel is manipulated after an engine is started, and activating a sleep mode if it is determined that the steering wheel is not manipulated and if a vehicle speed is lower than a reference value for activating the sleep mode, or if it is determined that the steering wheel is manipulated and if an amount of current conducted in a motor, a vehicle speed and a steering angular velocity are lower than respective reference values for a predetermined time. According to the method, it is possible to reduce current consumption when the steering wheel is not manipulated and improve the vehicular fuel efficiency.
摘要翻译：一种降低用于车辆的电动液压动力转向系统的消耗电力的方法包括：确定在发动机起动之后是否操纵方向盘，并且如果确定方向盘未被操纵，则启动睡眠模式，并且如果车速低于用于启动睡眠模式的参考值，或者如果确定方向盘被操纵，并且如果在电动机中传导的电流量，车速和转向角速度低于相应的参考值值预定时间。根据该方法，可以减少方向盘未被操纵时的电流消耗，并提高车辆燃料效率。

27. 发明申请

US20080191757A1 Delay locked loop circuit with duty cycle correction and method of controlling the same 失效
标题翻译：具有占空比校正的延迟锁定环路电路及其控制方法
公开(公告)号：US20080191757A1
公开(公告)日：2008-08-14
申请号：US11878244
申请日：2007-07-23
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/085 , H03K5/05 , H03L7/08
CPC分类号： H03K5/1565 , H03L7/0814 , H03L7/087
摘要： A delay locked loop block receives external clocks to generate first internal clocks including a reference clock. An internal delay unit delays the first internal clocks to output second internal clocks, which are fed back to the delay locked loop block. The delay locked loop block adjusts delay time of the delay unit according to a phase difference between each second internal clock and the reference clock so that the second internal clocks are delay locked. A duty cycle correcting block corrects a duty cycle of each second internal clock and outputs a duty cycle corrected clock. An error determining unit compares a phase of each second internal clock with one another and, based on the comparison, feeds back a feedback clock including one of the duty cycle corrected clock or the second internal clock to the delay locked loop block.
摘要翻译：延迟锁定环路块接收外部时钟以产生包括参考时钟的第一内部时钟。内部延迟单元延迟第一内部时钟以输出第二内部时钟，将其反馈到延迟锁定环路块。延迟锁定环路块根据每个第二内部时钟和参考时钟之间的相位差来调整延迟单元的延迟时间，使得第二内部时钟被延迟锁定。占空比校正块校正每个第二内部时钟的占空比，并输出占空比校正时钟。误差确定单元将每个第二内部时钟的相位彼此进行比较，并且基于比较，将包括占空比校正时钟或第二内部时钟中的一个的反馈时钟反馈到延迟锁定环路块。

28. 发明申请

US20080130384A1 Delay locked loop circuit 有权
公开(公告)号：US20080130384A1
公开(公告)日：2008-06-05
申请号：US12010964
申请日：2008-01-31
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： G11C7/00 , H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , H03L7/0805
摘要： A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.

29. 发明授权

US07125994B2 PNA monomer and precursor 有权
公开(公告)号：US07125994B2
公开(公告)日：2006-10-24
申请号：US11182672
申请日：2005-07-15
申请人： Sung Kee Kim , Hyunil Lee , Jong Chan Lim , Hoon Choi , Jae Hoon Jeon , Sang Youl Ahn , Sung Hee Lee , Won Jun Yoon
发明人： Sung Kee Kim , Hyunil Lee , Jong Chan Lim , Hoon Choi , Jae Hoon Jeon , Sang Youl Ahn , Sung Hee Lee , Won Jun Yoon
IPC分类号： C07D473/34 , C07D473/18 , C07D247/02 , C07D417/12 , C07D413/12
CPC分类号： C07D417/04 , C07B2200/11 , C07D277/80 , C07D417/12 , C07D417/14 , Y02P20/55
摘要： This application relates to monomers of the general formula (I) for the preparation of PNA (peptide nucleic acid) oligomers and provides method for the synthesis of both predefined sequence PNA oligomers and random sequence PNA oligomers: wherein E is nitrogen or C—R′; J is sulfur or oxygen; R′, R1, R2, R3, R4 is independently H, halogen, alkyl, nitro, nitrile, alkoxy, halogenated alkyl, halogenated alkoxy, phenyl or halogenated phenyl, R5 is H or protected or unprotected side chain of natural or unnatural α-amino acid; and B is a natural or unnatural nucleobase, wherein when said nucleobase has an exocyclic amino function, said function is protected by protecting group which is labile to acids but stable to weak to medium bases in the presence of thiol.

30. 发明申请

US20060008835A1 PNA monomer and precursor 有权
公开(公告)号：US20060008835A1
公开(公告)日：2006-01-12
申请号：US11182672
申请日：2005-07-15
申请人： Sung Kim , Hyunil Lee , Jong Lim , Hoon Choi , Jae Jeon , Sang Ahn , Sung Lee , Won Yoon
发明人： Sung Kim , Hyunil Lee , Jong Lim , Hoon Choi , Jae Jeon , Sang Ahn , Sung Lee , Won Yoon
IPC分类号： C12Q1/68 , C07D473/14
CPC分类号： C07D417/04 , C07B2200/11 , C07D277/80 , C07D417/12 , C07D417/14 , Y02P20/55
摘要： This application relates to monomers of the general formula (I) for the preparation of PNA (peptide nucleic acid) oligomers and provides method for the synthesis of both predefined sequence PNA oligomers and random sequence PNA oligomers: wherein E is nitrogen or C—R′; J is sulfur or oxygen; R′, R1, R2, R3, R4 is independently H, halogen, alkyl, nitro, nitrile, alkoxy, halogenated alkyl, halogenated alkoxy, phenyl or halogenated phenyl, R5 is H or protected or unprotected side chain of natural or unnatural α-amino acid; and B is a natural or unnatural nucleobase, wherein when said nucleobase has an exocyclic amino function, said function is protected by protecting group which is labile to acids but stable to weak to medium bases in the presence of thiol.

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