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21. 发明申请

US20080182359A1 TECHNIQUES FOR PROVIDING DECOUPLING CAPACITANCE 失效
标题翻译：提供去耦电容的技术
公开(公告)号：US20080182359A1
公开(公告)日：2008-07-31
申请号：US12056852
申请日：2008-03-27
申请人： Raymond R. Horton , John U. Knickerbocker , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Raymond R. Horton , John U. Knickerbocker , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L21/00
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译：提供电子器件制造技术。一方面，提供一种电子设备。电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。选择性地去激活多个去耦电容器中的一个或多个。

22. 发明申请

US20080116537A1 CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC 有权
标题翻译： CMOS图像阵列带有电介质
公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

23. 发明授权

US07052925B2 Method for manufacturing self-compensating resistors within an integrated circuit 有权
标题翻译：在集成电路内制造自补偿电阻的方法
公开(公告)号：US07052925B2
公开(公告)日：2006-05-30
申请号：US10709039
申请日：2004-04-08
申请人： William J. Murphy , Edmund J. Sprogis , Anthony K. Stamper , Erick G. Walton
发明人： William J. Murphy , Edmund J. Sprogis , Anthony K. Stamper , Erick G. Walton
IPC分类号： H01L31/26
CPC分类号： H01L28/20 , H01L27/0802 , Y10T29/49082 , Y10T29/49085
摘要： A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.
摘要翻译：公开了一种在集成电路内制造自补偿电阻器的方法。自补偿电阻器包括第一电阻器和第二电阻器。初始形成具有第一电阻值的第一电阻器，然后形成具有第二电阻值的第二电阻器。第二个电阻与第一个电阻串联。第二电阻值小于第一电阻值，但是第一和第二电阻器的总电阻值超过期望的目标电阻范围。最后，向第二电阻器发送电流以改变第二电阻器的尺寸，使得第一和第二电阻器的总电阻值落在期望的目标电阻范围内。

24. 发明授权

US06279815B1 Stacked chip process carrier 失效
标题翻译：堆叠芯片加工载体
公开(公告)号：US06279815B1
公开(公告)日：2001-08-28
申请号：US09621561
申请日：2000-07-21
申请人： George C. Correia , John E. Cronin , Edmund J. Sprogis
发明人： George C. Correia , John E. Cronin , Edmund J. Sprogis
IPC分类号： B23K3102
CPC分类号： H01L21/6835 , B23K37/0408 , B23K2101/40 , H01L25/50 , H01L2221/68313 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/30105 , Y10T29/53978 , H01L2924/00014
摘要： The present invention provides an apparatus and methods for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.
摘要翻译：本发明提供一种用于在与两个装置之间执行C4键的同时保持第一半导体器件与第一半导体器件的尺寸不同的第二半导体器件的正确对准的装置和方法。用于将两个装置保持正确对准的装置包括保持夹具，其包括用于接收半导体装置的上部和下部口袋容器。将半导体器件放置在与保持夹具的两个或更多个边缘对准的相应的上部和下部狭缝中。

25. 发明授权

US5534732A Single twist layout and method for paired line conductors of integrated circuits 失效
标题翻译：集成电路成对线导体的单扭曲布局和方法
公开(公告)号：US5534732A
公开(公告)日：1996-07-09
申请号：US567437
申请日：1995-12-04
申请人： John K. DeBrosse , Jenifer E. Lary , Edmund J. Sprogis
发明人： John K. DeBrosse , Jenifer E. Lary , Edmund J. Sprogis
IPC分类号： H01L21/822 , G11C7/18 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/108 , H01L27/10
CPC分类号： H01L27/108 , G11C7/18 , H01L23/5225 , H01L2924/0002 , Y10S257/907
摘要： An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.
摘要翻译：为主要平行延伸的给定长度的多个成对线导体提供互连阵列布局和方法。单个交叉区域穿过给定长度中间的成对线导体，其中每对线路导体的线路导体互相交叉，使得对间电容耦合相匹配。通过将每对线路导体的线路导体分开两个间距并在其间设置不同对线路导线的线路导体来避免对内电容耦合。应用包括诸如DRAM结构的半导体存储器阵列，以及使用配对的真/互补线导体的地址/数据总线。

26. 发明授权

US5303196A Open bit line memory devices and operational method 失效
标题翻译：打开位线存储器件和操作方法
公开(公告)号：US5303196A
公开(公告)日：1994-04-12
申请号：US888226
申请日：1992-05-22
申请人： Hoo D. Sang , Edmund J. Sprogis
发明人： Hoo D. Sang , Edmund J. Sprogis
IPC分类号： G11C11/401 , G11C7/06 , G11C7/18 , G11C11/4091 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/18 , G11C11/4091 , G11C7/06
摘要： An open bit line memory device and operational method are provided having performance characteristics commensurate with those of folded bit line architecture. The memory device includes a plurality of memory cells in open bit line configuration, at least some of which are interconnected by a bit line. A sense amplifier unit is coupled to the bit line for sensing a developing signal thereon during a predefined bit line signal development interval. The amplifier sets to one of two logical states during a subsequent setting interval. An electrical isolator is employed to decouple the bit line from the sense amplifier during the setting interval so that signal variations on the bit line do not effect the amplifier. Each bit line also has an associated reference voltage line, and the electrical isolator isolates both the bit line and the associated reference voltage line from the sense amplifier during amplifier's setting period.
摘要翻译：提供了一种开放位线存储器件和操作方法，其具有与折叠位线架构相匹配的性能特征。存储器件包括开放位线配置的多个存储器单元，其中至少一些由位线互连。感测放大器单元耦合到位线，以在预定义的位线信号发展间隔期间感测其上的显影信号。放大器在随后的设置间隔期间设置为两个逻辑状态之一。采用电隔离器在设定间隔期间将位线与读出放大器去耦，使位线上的信号变化不影响放大器。每个位线还具有相关联的参考电压线，并且电隔离器在放大器的设置周期期间将位线和相关联的参考电压线与读出放大器隔离。

27. 发明授权

US09406562B2 Integrated circuit and design structure having reduced through silicon via-induced stress 有权
标题翻译：集成电路和设计结构通过硅通孔引起的应力降低
公开(公告)号：US09406562B2
公开(公告)日：2016-08-02
申请号：US13005883
申请日：2011-01-13
申请人： Jeffrey P. Bonn , Brent A. Goplen , Brian L. Kinsman , Robert M. Rassel , Edmund J. Sprogis , Daniel S. Vanslette
发明人： Jeffrey P. Bonn , Brent A. Goplen , Brian L. Kinsman , Robert M. Rassel , Edmund J. Sprogis , Daniel S. Vanslette
IPC分类号： H01L23/48 , H01L21/768 , G06F17/50
CPC分类号： H01L21/76898 , G06F17/5068 , G06F2217/80 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.
摘要翻译：本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

28. 发明授权

US08198734B2 Silicon-on-insulator structures for through via in silicon carriers 有权
标题翻译：硅载体中的通孔绝缘体上硅结构
公开(公告)号：US08198734B2
公开(公告)日：2012-06-12
申请号：US12550494
申请日：2009-08-31
申请人： Brent A. Anderson , Paul S. Andry , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Brent A. Anderson , Paul S. Andry , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L27/12 , H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L21/486 , H01L21/6835 , H01L21/76898 , H01L21/84 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L2221/68368 , H01L2221/68372 , H01L2224/0231 , H01L2224/02313 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/16146 , H01L2224/81005 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/01019 , H01L2924/09701 , H01L2924/10253 , H01L2924/12044 , H01L2924/19041 , H01L2924/19043
摘要： A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.
摘要翻译：提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括用一层掩埋氧化物结合到硅衬底结构的硅晶片载体结构和分离这些硅结构的氮化物层。在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。通孔填充有多晶硅或导电材料的填充材料。然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。然后通孔用导电材料回填。

29. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

30. 发明授权

US08166651B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08166651B2
公开(公告)日：2012-05-01
申请号：US12181359
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
摘要翻译：一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

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