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21. 发明授权

US08728895B1 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08728895B1
公开(公告)日：2014-05-20
申请号：US14146528
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/336
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

22. 发明申请

US20140120679A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：双重扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140120679A1
公开(公告)日：2014-05-01
申请号：US14146528
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/28 , H01L29/66
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

23. 发明授权

US09362384B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09362384B2
公开(公告)日：2016-06-07
申请号：US14559542
申请日：2014-12-03
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

24. 发明申请

US20120241870A1 Bipolar junction transistor with surface protection and manufacturing method thereof 审中-公开
标题翻译：具有表面保护的双极结晶体管及其制造方法
公开(公告)号：US20120241870A1
公开(公告)日：2012-09-27
申请号：US13373225
申请日：2011-11-08
申请人： Chien-Ling Chan , Yuh-Chyuan Wang , Hung-Der Su
发明人： Chien-Ling Chan , Yuh-Chyuan Wang , Hung-Der Su
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L29/7322 , H01L27/0623 , H01L27/1052 , H01L29/66272
摘要： The present invention discloses a bipolar junction transistor (BJT) with surface protection and a manufacturing method thereof. The BJT includes: a first conductive type base, a second conductive type emitter, and a second conductive type collector, which are formed in a substrate, wherein the base is formed between and separates the emitter and the collector, and the base includes a base contact region functioning as an electrical contact node of the base; and a gate structure which is formed on the substrate between the base contact region and the second conductive type emitter.
摘要翻译：本发明公开了一种具有表面保护的双极结型晶体管（BJT）及其制造方法。 BJT包括：形成在基板中的第一导电型基极，第二导电型发射极和第二导电型集电极，其中基极形成在发射极和集电极之间并分离，并且基极包括基极接触区域用作基座的电接触节点; 以及栅极结构，其形成在所述基极接触区域和所述第二导电型发射极之间。

25. 发明授权

US07768033B2 Single-chip common-drain JFET device and its applications 有权
公开(公告)号：US07768033B2
公开(公告)日：2010-08-03
申请号：US12385720
申请日：2009-04-17
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

26. 发明授权

US07759695B2 Single-chip common-drain JFET device and its applications 失效
标题翻译：单片共漏极JFET器件及其应用
公开(公告)号：US07759695B2
公开(公告)日：2010-07-20
申请号：US12385717
申请日：2009-04-17
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要翻译：单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

27. 发明授权

US07535032B2 Single-chip common-drain JFET device and its applications 失效
标题翻译：单片共漏极JFET器件及其应用
公开(公告)号：US07535032B2
公开(公告)日：2009-05-19
申请号：US11165028
申请日：2005-06-24
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要翻译：单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

28. 发明申请

US20080153239A1 Semiconductor process for butting contact and semiconductor circuit device having a butting contact 审中-公开
标题翻译：用于对接接触的半导体工艺和具有对接接触的半导体电路器件
公开(公告)号：US20080153239A1
公开(公告)日：2008-06-26
申请号：US11805979
申请日：2007-05-25
申请人： Hung-Der Su , Ching-Yao Yang , Chien-Ling Chan
发明人： Hung-Der Su , Ching-Yao Yang , Chien-Ling Chan
IPC分类号： H01L21/336 , G03F1/00
CPC分类号： H01L21/823475 , H01L21/26586 , H01L21/76895 , H01L21/823425
摘要： According to the present invention, a semiconductor process for butting contact comprises: providing a substrate on which are formed two adjacent transistor gates; implanting a full area between the two adjacent transistor gates by a tilt angle, to form a lightly doped region of a first conductivity type; forming a heavily doped region of the first conductivity type and a heavily doped region of a second conductivity type in the area between the two adjacent transistor gates, in which the heavily doped region of the second conductivity type overrides the lightly doped region of the first conductivity type, and divides the heavily doped region of the first conductivity type into two areas; depositing a dielectric layer; and forming a butting contact in the dielectric layer which concurrently contacts the two divided heavily doped regions of the first conductivity type.
摘要翻译：根据本发明，用于对接接触的半导体工艺包括：提供在其上形成两个相邻晶体管栅极的衬底; 在两个相邻的晶体管栅极之间以倾斜角注入全部区域，以形成第一导电类型的轻掺杂区域; 在所述两个相邻晶体管栅极之间的区域中形成第一导电类型的重掺杂区域和第二导电类型的重掺杂区域，其中所述第二导电类型的重掺杂区域覆盖所述第一导电类型的轻掺杂区域并且将第一导电类型的重掺杂区域划分为两个区域; 沉积介电层; 以及在同时接触第一导电类型的两个分开的重掺杂区域的电介质层中形成对接触点。

29. 发明申请

US20070176636A1 Power supply circuit and control method thereof 有权
标题翻译：电源电路及其控制方法
公开(公告)号：US20070176636A1
公开(公告)日：2007-08-02
申请号：US11650525
申请日：2007-01-08
申请人： Jing-Meng Liu , Hung-Der Su
发明人： Jing-Meng Liu , Hung-Der Su
IPC分类号： H03K19/0175
CPC分类号： H02M3/156
摘要： A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.
摘要翻译：提供了电源电路和控制方法，其中原始使能焊盘和输出焊盘或使能焊盘和反馈焊盘用于修剪电源电路的输出电压而无需额外的修整焊盘。

30. 发明申请

US20060214648A1 Control apparatus and method for a boost-inverting converter 有权
标题翻译：升压反相转换器的控制装置和方法
公开(公告)号：US20060214648A1
公开(公告)日：2006-09-28
申请号：US11388158
申请日：2006-03-24
申请人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
发明人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
IPC分类号： G05F1/00
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.
摘要翻译：多个开关，电感器和两个电容器被配置为升压反相转换器。为了在升压反转模式下操作转换器，控制装置和方法切换开关使得电感器在第一相中通电，第一电容器被放电以在第二相中产生反相电压，并且第二电容器充电以在第三相中产生升压电压。因此，升压反相转换器具有较低的峰值电感电流和较小的功率损耗，并且对升压反相转换器的开关设计的限制放宽。

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