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21. 发明专利

JP2004214471A Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：JP2004214471A
公开(公告)日：2004-07-29
申请号：JP2003000842
申请日：2003-01-07
申请人： Nec Corp , 日本電気株式会社
发明人： OKAMOTO YASUHIRO , MIYAMOTO HIRONOBU , ANDO YUJI , NAKAYAMA TATSUO , INOUE TAKASHI , KUZUHARA MASAAKI
IPC分类号： H01L29/812 , H01L21/338 , H01L29/06 , H01L29/20 , H01L29/40 , H01L29/778 , H01L29/80
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/7787
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor excellent in a balance of collapse and gate withstand voltage.
SOLUTION: An electric field control electrode 5 is formed between a gate electrode 2 and a drain electrode 3. A laminate film composed of an SiN film 21 and an SiO
2 film 22 is formed under the field effect control electrode 5. The SiN film 21 is formed to cover the surface of an AlGaN electron supply layer 13.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供在塌陷和栅极耐受电压平衡方面优异的场效应晶体管。解决方案：在栅极电极2和漏极电极3之间形成电场控制电极5.由SiN膜21和SiO 2 膜22构成的层压膜形成在场效应控制电极5. SiN膜21形成为覆盖AlGaN电子供给层13的表面。版权所有（C）2004，JPO＆NCIPI

22. 发明专利

JPH08204410A POWER DISTRIBUTOR/SYNTHESIZER 失效
公开(公告)号：JPH08204410A
公开(公告)日：1996-08-09
申请号：JP1135695
申请日：1995-01-27
申请人： NEC CORP
发明人： INOUE TAKASHI
IPC分类号： H01P5/02 , H01P5/19
摘要： PURPOSE: To exclude the deterioration of power distributing/synthesizing characteristic even when the value of absorption resistor is deviated from a preset value. CONSTITUTION: An impedance converter 10 which sets impedance Za at Z0 /2

23. 发明专利

JPH07169911A INTER DIGITAL CAPACITOR 失效
公开(公告)号：JPH07169911A
公开(公告)日：1995-07-04
申请号：JP31621193
申请日：1993-12-16
申请人： NEC CORP
发明人： HOSOYA KENICHI , INOUE TAKASHI
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To fix a distance from an input power supply terminal to an output power supply terminal without increasing an occupancy area and a propagation distance without depending on a route and avoiding high frequency characteristics deteriorated resultant from a phase difference. CONSTITUTION:This invention relates to an interdigital capacitor which connects an input power supply terminal 1 to the end of an input connection electrode 3 and connects an output power supply terminal 2 to the end of an output connection electrode 4 which is the opposite side of the input power supply terminal 1. This construction makes it possible to fix the distance from the input power supply terminal 1 to the output power supply terminal 2 without increasing an occupancy area or a signal propagation distance not based on its route and avoid high frequency characteristics deteriorated resultant from a phase difference.

24. 发明专利

JP2010283048A Heterojunction field-effect transistor and method of manufacturing the same 有权
标题翻译：异相场效应晶体管及其制造方法
公开(公告)号：JP2010283048A
公开(公告)日：2010-12-16
申请号：JP2009133733
申请日：2009-06-03
申请人： Nec Corp , 日本電気株式会社
发明人： INOUE TAKASHI , NAKAYAMA TATSUO , ANDO YUJI , OKAMOTO YASUHIRO , OTA KAZUKI , MIYAMOTO HIRONOBU
IPC分类号： H01L29/80 , H01L21/336 , H01L21/338 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7788 , H01L29/0657 , H01L29/2003 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide a heterojunction field-effect transistor that eliminates various faults while improving a device structure so that a traveling direction of an electron below a gate electrode is substantially parallel with a substrate surface. SOLUTION: An n-type conductive layer is formed by activating a selectively ion-implanted n-type impurity such as silicon (Si) by annealing, and the n-type conductive layer has ions implanted with acceleration energy of ≥200 keV and is formed through selective ion implantation such that implanted ions reach a semiconductor layer deeper than a p-type nitride semiconductor layer and electrically connecting with a drain electrode 114, a concentration of the n-type impurity implanted into a connection part 115 between the n-type conductive layer and a channel region where the n-type impurity is not implanted being ≤1×10 18 cm -3 . COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种异质结场效应晶体管，其在改善器件结构的同时消除各种故障，使得栅电极下方的电子的行进方向基本上平行于衬底表面。解决方案：通过退火激活选择性离子注入的n型杂质如硅（Si）形成n型导电层，n型导电层具有注入加速能≥200keV的离子并且通过选择性离子注入形成，使得注入的离子到达比p型氮化物半导体层更深的半导体层并与漏电极114电连接，n型杂质的浓度注入在n n型导电层和n型杂质不被注入的沟道区域为≤1×10 18 cm -3 。版权所有（C）2011，JPO＆INPIT

25. 发明专利

JP2010245268A Field effect transistor, and manufacturing method of field effect transistor 有权
标题翻译：场效应晶体管和场效应晶体管的制造方法
公开(公告)号：JP2010245268A
公开(公告)日：2010-10-28
申请号：JP2009092109
申请日：2009-04-06
申请人： Nec Corp , 日本電気株式会社
发明人： INOUE TAKASHI , ANDO YUJI , NAKAYAMA TATSUO
IPC分类号： H01L21/338 , H01L21/283 , H01L21/314 , H01L29/41 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To improve an increase of an on-resistance and an increase of a current collapse in a field effect transistor.
SOLUTION: The field effect transistor includes a semiconductor structure including a first semiconductor layer 6 and a second semiconductor layer 4 in heterojunction with the first semiconductor layer 6, a source electrode 8, a drain electrode 10, a gate electrode 9, each formed on the first semiconductor layer 6, and a protective film 11 including at least a metal-doped fullerene formed on the first semiconductor layer 6. A material of the protective film 11 may be a mixture of the metal-doped fullerene and an insulating material, or a mixture of the metal-doped fullerene and non-metal doped fullerene.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了改善场效应晶体管中导通电阻的增加和电流崩溃的增加。解决方案：场效应晶体管包括半导体结构，其包括与第一半导体层6异质结的第一半导体层6和第二半导体层4，源电极8，漏电极10，栅电极9，各自形成在第一半导体层6上的保护膜11和至少包含在第一半导体层6上形成的掺杂金属的富勒烯的保护膜11.保护膜11的材料可以是金属掺杂的富勒烯和绝缘材料的混合物，或金属掺杂的富勒烯和非金属掺杂的富勒烯的混合物。版权所有（C）2011，JPO＆INPIT

26. 发明专利

JP2010135399A Hetero junction field effect transistor and manufacturing method thereof 有权
标题翻译：异位连接场效应晶体管及其制造方法
公开(公告)号：JP2010135399A
公开(公告)日：2010-06-17
申请号：JP2008307644
申请日：2008-12-02
申请人： Nec Corp , 日本電気株式会社
发明人： INOUE TAKASHI , MIYAMOTO HIRONOBU , OTA KAZUKI , NAKAYAMA TATSUO , OKAMOTO YASUHIRO , ANDO YUJI
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a hetero junction field effect transistor which reduces contact resistance between an n+ layer region of a source electrode and a drain electrode and a 2DEG channel. SOLUTION: The hetero junction field effect transistor includes an electron traveling layer formed on a substrate, an electron supply layer formed on the electron traveling layer, and a trench provided on the electron supply layer corresponding to each of a source electrode and a drain electrode. The bottom surface of the trench is away from a hetero-junction which is the interface between the electron traveling layer and the electron supply layer by only a predetermined distance. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低源电极的n +层区域和漏极电极与2DEG通道之间的接触电阻的异质结场效应晶体管。异质结场效应晶体管包括形成在基板上的电子传输层，形成在电子传播层上的电子供给层和设置在电子供给层上的与源电极和漏电极。沟槽的底表面远离作为电子传播层和电子供给层之间的界面的异质结只有预定的距离。版权所有（C）2010，JPO＆INPIT

27. 发明专利

JP2010016105A HEAT TREATMENT METHOD FOR GaN-BASED DEVICE ON Si SUBSTRATE 有权
标题翻译： Si衬底上GaN基器件的热处理方法
公开(公告)号：JP2010016105A
公开(公告)日：2010-01-21
申请号：JP2008173538
申请日：2008-07-02
申请人： Nec Corp , 日本電気株式会社
发明人： INOUE TAKASHI , NAKAYAMA TATSUO , MIYAMOTO HIRONOBU
IPC分类号： H01L21/265 , H01L21/28
摘要： PROBLEM TO BE SOLVED: To provide a method of performing an annealing treatment while suppressing sublimation or the like of an Si substrate during activation annealing of a GaN-based semiconductor on the Si substrate. SOLUTION: The entire surface of a sample having the GaN-based semiconductor formed on the Si substrate is coated with a protective film which is stable at a heat treatment temperature, for example, Si 2 O x N y (0 COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在Si衬底上的GaN基半导体的活化退火期间抑制Si衬底的升华等的同时进行退火处理的方法。解决方案：在Si衬底上形成的具有GaN基半导体的样品的整个表面涂覆有在热处理温度下稳定的保护膜，例如Si 2 < （0

28. 发明专利

JP2009246247A Nitride semiconductor transistor 有权
标题翻译：氮化物半导体晶体管
公开(公告)号：JP2009246247A
公开(公告)日：2009-10-22
申请号：JP2008093067
申请日：2008-03-31
申请人： Nec Corp , 日本電気株式会社
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , NAKAYAMA TATSUO , OKAMOTO YASUHIRO , OTA KAZUKI , INOUE TAKASHI
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a normally-off type field effect transistor that is used for a power control device in which a drain current density equivalent to a high-frequency transistor in an on-state is available and a forward leakage current density of a gate electrode is suppressed when a positive voltage of 10-volt is applied to the gate electrode. SOLUTION: A field effect transistor is produced. It adopts an MIS-type structure in which a gate electrode is provided on the surface of an electron supply layer consisting of a nitride semiconductor through an insulation film to suppress a forward leakage current density of the gate electrode. A drain electrode has such a structure that an ohmic contact is formed on a p-type nitride semiconductor layer formed on the surface of the electron supply layer. The field effect transistor has a function to inject holes from the drain electrode portion into a channel layer beyond the electron supply layer in an on-state during a high-voltage operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于功率控制装置的常关型场效应晶体管，其中等效于处于导通状态的高频晶体管的漏极电流密度可用，并且正向泄漏当对栅电极施加10伏的正电压时，抑制栅电极的电流密度。解决方案：产生场效应晶体管。采用MIS型结构，其中通过绝缘膜在由氮化物半导体构成的电子供给层的表面上设置栅极，以抑制栅电极的正向漏电流密度。漏电极具有在形成在电子供给层的表面上的p型氮化物半导体层上形成欧姆接触的结构。场效应晶体管具有在高电压操作期间将导通状态的漏极电极部分的空穴注入超过电子供给层的沟道层的功能。版权所有（C）2010，JPO＆INPIT

29. 发明专利

JP2009206396A Field-effect transistor and manufacturing method thereof 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：JP2009206396A
公开(公告)日：2009-09-10
申请号：JP2008049367
申请日：2008-02-29
申请人： Nec Corp , 日本電気株式会社
发明人： INOUE TAKASHI , YAMANOGUCHI KATSUMI , ANDO YUJI , OKAMOTO YASUHIRO , MIYAMOTO HIRONOBU
IPC分类号： H01L29/80 , H01L21/027 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To solve a problem that, in an epitaxy for GaN-based or GaAs-based FET, there is recently a trend using a high-resistance epitaxy for a buffer layer in order to improve a withstand voltage of the buffer layer, but a charge-up phenomenon is generated during lithography by electron beam exposure for the patterning of a fine gate.
SOLUTION: A path for electrons to be discharged is formed by metal wiring. More specifically, the metal wiring is arranged in a portion corresponding to a scribe line or an etch cut portion of a peripheral portion of each chip on a wafer on which an FET is manufactured, a portion which serves as a positive electrode or a grounding conductor for an electron beam on the wafer and the metal wiring are connected by metal, and furthermore, in a chip, a source electrode of the FET is made to be connected to the metal wiring around the chip by metal.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题为了解决在GaN系或GaAs系FET的外延中存在的问题，为了提高缓冲层的耐电压性，近来存在使用高电阻外延的趋势缓冲层，但是通过用于精细栅极图案化的电子束曝光在光刻期间产生电荷现象。解决方案：通过金属布线形成电子放电的路径。更具体地说，金属布线被布置在对应于在其上制造FET的晶片上的每个芯片的周边部分的划线或蚀刻切割部分的部分，用作正极的部分或接地导体对于晶片上的电子束和金属布线通过金属连接，此外，在芯片中，通过金属将FET的源电极连接到芯片周围的金属布线。版权所有（C）2009，JPO＆INPIT

30. 发明专利

JP2008306083A Iii-v nitride semiconductor field-effect transistor and its manufacturing method 审中-公开
标题翻译： III-V氮化物半导体场效应晶体管及其制造方法
公开(公告)号：JP2008306083A
公开(公告)日：2008-12-18
申请号：JP2007153537
申请日：2007-06-11
申请人： Nec Corp , 日本電気株式会社
发明人： WAKEJIMA AKIO , MIYAMOTO HIRONOBU , INOUE TAKASHI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , KURODA NAOTAKA , OTA KAZUKI , TANOMURA MASAHIRO , MURASE YASUHIRO , ANDO YUJI
IPC分类号： H01L21/338 , H01L21/28 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide an FET which suppresses current collapse, relaxes an electric field generated at a drain side edge of a gate, and is operable at a high voltage.
SOLUTION: A GaN buffer layer 102 and an AlGaN layer 103 are formed on a substrate 101. A source electrode 104 and a drain electrode 105 are formed on a surface of the AlGaN layer 103. Space between the source electrode 104 and the drain electrode 105 is covered by an SiN film 106. An opening is formed in the SiN film 106, while a recess is done in the AlGaN layer 103, and a gate electrode 107 is formed burying the opening and the recess. A bottom face portion of the gate electrode 107 includes a bottom flat portion 201 parallel to an AlGaN layer/GaN layer interface, and an inclination changing portion 202 not parallel to the interface. In a curve of the inclination changing portion 202, a slope of a tangent line changes continuously, and forms a projected shape downward.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种抑制电流崩溃的FET，可以松弛在栅极的漏极侧边缘处产生的电场，并且可以在高电压下工作。解决方案：在衬底101上形成GaN缓冲层102和AlGaN层103.源电极104和漏极105形成在AlGaN层103的表面上。源电极104和漏电极105被SiN膜106覆盖。在AlGaN层103中进行凹陷时，在SiN膜106中形成开口，并且形成埋入开口和凹部的栅电极107。栅电极107的底面部分包括平行于AlGaN层/ GaN层界面的底部平坦部分201和不与界面平行的倾斜改变部分202。在倾斜变化部分202的曲线中，切线的斜率连续变化，并且向下形成投影形状。版权所有（C）2009，JPO＆INPIT

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